The good news is that Phenom is confirmed to launch next month (probably Nov 30 2007). The bad news is 2.4Ghz is the best AMD can come up with while it gets beaten to market by Intel's 45nm SKUs. Setting it up against Intel's QX6850 at 3Ghz, anyone would think it's a bit inhumane and sadistic to run a side by side comparison when AMD is in a big and embarrasing disadvantage.
2.6GHz is expected to ship on the last working day of this year (Dec 2007) while anything higher including the FX chips will arrive sometime in spring. In a manner typical of AMD, its Desktop parts appears to be delayed and expected to be underwhelming even before launch. We can only expect another round of horrible benchmark comparisons for AMD, in most cases left trying to compete with its own Athlon FX CPUs, never mind trying to beat Intel's Core2. Phenom's poor showing should stifle the hope anyone may yet have, thinking that K10 will retake any kind of meaningful leadership.
Based on our experience with the Barcelona launch and the relatively low speed of Phenom, we can expect this to be another paper launch, only meant to save face due to competitive reasons. If you're one of those loyal enough to buy inferior products to support the underdog, don't expect to get hold of these until next year.
Phenom 9 Series
9500 - 2.2Ghz - 89W - Nov 2007
9600 - 2.4Ghz - 89W - Nov 2007
9700 - 2.6Ghz - 125W - Dec 2007
9xxx - >2.6Ghz - Q2 2008 <- performance wall?
Phenom FX
FX82 - 2.6Ghz - Q1 2008
FX8X - Q2 2008
10.10.2007
Phenom Problem
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77 comments:
Resistance was futile! I capitulated to the call. Sadly, I pulled the 955EE out of my machine and swapped the chips. (I pulled the swap without her knowledge, of course.) Slapped the Q6600 into the P5WDG2-WS-PRO with stealth like precision, and VIOLA! Ayatollah, of Rockn’ Rolla! The benchies FLEW off the charts! HOOYA! 3d-MARK ’06 @ 11350! 95% percentile (14952 Ranked)! (Crossfire 1900XTX setup) This was a 276 dollar upgrade on an 18 month old machine! Best upgrade since a 486DX-33 from a 386-40, bar none.
Indeed! I pulled my E6600 out of my P5B Deluxe about six months ago and put a Q6600 in. The results were just crazy. I can run two video encodes at once while rendering in Houdini. The system is nearly twice as fast as my E6600 when doing this sort of multitasking. In games there's not much difference from the E6600 (Supreme Commander is the exception) but the E6600 already delivered an AWESOME gaming experience (My card is a single XFX 8800 GTS XXX 640MB).
For $280? It's about the best buy one can make now! One thing is for sure, Yorkfield with 1600mhz FSB, 12MB L2 cache and SSE4 is just going to scream!
By the way, your above comment is law!
Absolutely. The price/performance of the Q6600 is unbeatable.
I read Roborat's latest entry with great interest. As we've seen from the current single threaded Barcelona performance, a 2.6Ghz Phenom will be no faster than the current $280 2.4Ghz Kentsfield Q6600.
Roborat, your 2008 projection dates show "2007" instead. I only wish that AMD had shipped Phenom early this year. =)
I don't have any allegiances to hardware or software companies, I will buy and use what works best for me. But this news is depressing. I've used a lot of good AMD CPUs over the years, and it's sad to see them struggling the way they are lately.
A direct yet modified copy of someone's 2007 top development article into here:
It now appears that AMD will only release limited if not paper-launched quadcore desktop chip in 2007 and it will only be clocked at 2.6Ghz. The chip draws a whopping 125 Watts. Thus we clearly see AMD's straining to deliver something faster much as Intel did since last year.
yeah, I fully understand the TDP is for a series of CPUs, but I just modified the above paragraph minimally from someone's article.
thanks for the correct Tonus!
... I myself is waiting for Yorkfield. I don't mind the wait while MS fixes Vista.
For posterity:
Scientia
If AMD can't release a 3.0Ghz quad in Q1 08 then there is a problem.
Even if AMD could release Agena at 3.0 GHz in Q1 08 in volume, I doubt this would restore them to profitability. Based on Anandtech, Tech Reports, and the recent SPEC single-thread disclosures by AMD, we know now that Agena 3.0 GHz will roughly compare in desktop performance to a 2.66 GHz Yorkfield. The latter is predicted to be priced at $316. Therefore AMD's entire quadcore Agena line would have to be priced at $316 and below to have fair market value. This will not raise AMD's ASPs sufficiently to counteract their furious cash burn rate.
I think the biggest news is not the quad cores, it's the dual core push out - these were expected to start trickling out at end of the year and now it appears they are set for a Q2'08 launch (whatever the heck AMD means by launch these days). They also appear to be suffering from the same clpckspeed malaise of the initial Barcy's.
The quads are the sizzle (or in this case fizzle), the duallies are the steak (or in this case hamburger).
That means the recent price cuts on the K8 desktops WERE NOT to clear inventory as everyone speculated - you would not clear inventory 2-3 quarters in advance of a launch (especially as it's not like AMD will ne 100% K10 starting at launch).
To me this indicates the K8 desktops, notwithstanding the PHENOMenal (pun intended) "black edition" marketing, are not moving and AMD needs to slash prices to move product and/or prevent more market erosion. If you look at the list prices, just think about what OEM's like Dell must be getting these chips for!
Scientia I'm sure will claim that this is more 65nm cost savings - but a company 1.2Bil in the hole in 2007 would pocket the extra cash if they were reducing the costs, no? Or perhaps this discussion takes place at AMD:
'Hey Hector, as we've been maturing 65nm and migrating more volume to this process, our average unit cost has gone down.'
Hector: 'Great now we can pass those savings on to the consumer because, we are nothing if not consumer friendly - not like that evil empire Intel!'
'But Hector, shouldn't we maybe hold the prices so we can slowly start getting out of debt by making a little more money on each chip and try to get back to profitability?'
Hector: 'PROFITABILITY?!? Hah, that's a good one! I'll just go back and sell some more convertibles'
(Everyone laughs)
Gentlemen, (And you know who I am addressing) In addition to the Pheromones stated, and now quite obvious problems, on a more technical level, what about thermals?
All of you, in the know, (pun intended) at one time or another has mentioned this would be a big limitation in the chips present incarnation. From what I gather, in addition 65nM and SOI being the limiting factor, can the design itself also be a factor. If so, can it be corrected? Even if it were, is it possible, from your experience, will these chips ever see 3 GHz? Further, compared to the present thermals and speeds, can it be calculated by some Guru (pun intended) method, what wattage are they looking at a hypothetical 3 GHz? Or was the Doc correct in saying months ago this thing was D.O.A.. All things considered.
SPARKS
"That means the recent price cuts on the K8 desktops WERE NOT to clear inventory as everyone speculated - you would not clear inventory 2-3 quarters in advance of a launch"
Unless they have 2-3 quarters worth of CPUs sitting in warehouses. Though I highly doubt that.
Another thing about those dualcores is that if they get launched as late as Q2 then when will 45nm CPUs be launched? At the moment I wouldn't be surprised if it happened in 2009.
"Another thing about those dualcores is that if they get launched as late as Q2 then when will 45nm CPUs be launched? At the moment I wouldn't be surprised if it happened in 2009."
Come on this is like the end of the year/launch crap AMD pulled on 65nm...oh we meant shipping to OEM's by end of year not actual product availability.
If you look at AMD words carefully they have stated they will be producing 45nm in H2'07 (they may have said mid-2007?) Producing from start to finsish takes ~4 months so if they are referring to production starts...let's put together a hypothetical timeline:
Production starts - July 1
Wafers out of fab - ~Oct 1
Slice/dice/package real nice - Nov1
OEM's actually have product to sell ~Dec 1
...and this would be the first trickle of 45nm chips. Of course AMD could mean actual part shipments in H2'07 and they would have then factored in production timeline. The bottom line is AMD has been so POOR at planning that they play with the verbage - why not just give a PRODUCT AVAILABILITY timeline?
I would expect AMD to focus 45nm on server first - this would likely help somewhat on thermal due to the lower Vt on the 45nm process and may allow AMD a speed bin or two. Of course with their CTI process where the initial 45nm transistor is basically the same as a 65nm and with the lack of highK/metal gate, it is questionable how much 45nm will be better for AMD from a technical perspective (of course they will get the economic benefit of shrinking the die).
"Unless they have 2-3 quarters worth of CPUs sitting in warehouses. Though I highly doubt that."
They don't - I think inventory was ~1 Bil (too lazy to look it up) - this would be ~ 1 quarter of sales, however keep in mind inventory is not just finished goods it includes raw materials and wafers partially in progress at the time of the end of quarter. If you also factor in it is impossibel to tell how much of the inventory is server vs DT vs mobile... there is still no way they have that much dual core desktop inventory - the pricing (in my view) has to be to stimulate demand.
"If you look at AMD words carefully they have stated they will be producing 45nm in H2'07"
I assume you meant 08 there.
"I would expect AMD to focus 45nm on server first - this would likely help somewhat on thermal due to the lower Vt on the 45nm process and may allow AMD a speed bin or two."
Are you sure? If things are similar to 65nm then they should use 45nm just for lower power usage with higher clock speeds coming (much) later.
"the pricing (in my view) has to be to stimulate demand."
I'm afraid so. It will definitely not help with their ASP.
"Further, compared to the present thermals and speeds, can it be calculated by some Guru (pun intended) method, what wattage are they looking at a hypothetical 3 GHz?"
Pretty difficult without some specific inside knowledge. My guess would be future steppings will still be adding in some 65nm process improvements from AMD's CTI approach (remember AMD's process is far from technically mature at the start of their ramp, unlike Intel). It's also a question of binsplits and how much process variability AMD has. The lower AMD sets the 3.0 GHz TDP, the more 2.8GHz parts AMD will have when they can't meet that bin with that thermal across the entire wafer.
If I were to venture a guess I would say 125 Watt (to enable better binsplits of the theoretical 3.0GHz parts) with an outside shot of dropping it down to their next regular bin (is that 89Watt?) - or they may pull the crap of an energy efficient version, which are mysteriously hard to find (because there bin splist are so low!).
The 45nm process should get this down to 89Watt or lower from the lower Vt's on 45nm (this is obviously dependent on what AMD does on their initial 45nm process rev)
As for SOI - the purported power consumption improvements is a terribly misunderstood and misreported fact. First off I think AMD is still using a partially depleted process on 65nm as opposed to a fully depleted process. An FD-SOI process allows for complete transistor (kind of) isolation and allows you to tailor other process steps better for power.
The main sources of power for transistors are:
Transistor on:
Idsat, and Vcc (input voltage); the other factor here is Vt, which is the threshold voltage - the lower this is the lower your input voltage could be and thus lower active power (the tradeoff with a low Vt device is that it tend to be leakier). The end user see this when they look at CPUZ and see the voltage # lower with newer nodes (generally) - if you track closely you'll also see this # sometimes creeps up on the higher speed bin pats within a given node. Idsat is driven by HUNDREDS of process variables, that I couldn't even begin to get into.
Transistor off:
1) Subthrshold leakage - this is leakage between the source and drain of the transistor as they are so close (and as this is transistor length dependent this leakage variable tends to grow with each node shrink). Also as you lower the Vt (to enable lower Vcore), Isub tends to increase as well. SOI does not address this directly (indirectly SOI may allow you to tailor halo, well and Vt adjust implants to help out a bit over a bulk Si process)
2) Gate leakage - this is driven by your gate oxide type (hence the move to high K) and thickness (and as thickness is scaled with each node this leakage parameter also tends to grow). SOI does nothing/very little for gate leakage. Gate leakage is one reason why AMD is targetting rather modest (some would say low) 20% performance gains going from 65 to 45nm. It is difficult to get large gains without scaling the gate oxide, but without high K you can't scale the gate oxide without leakage exploding (gate leakage is exponentially dependent on gate thickness)
3)Finally, in a DISTANT 3rd you have junction leakage or leakage to the substrate and this is the main area that SOI directly addresses, however it is by far the smallest component of leakage and there are many tricks you can play to minimize this impact on bulk Si (things like compensation or retrograde implants, anneal profiles also come into play)... of course lost in all of this is the fact that an additional implant step or two is FAR CHEAPER than the added SI substrate cost, though the engineering on the bulk Si process is by no means trivial.
The main problem with the press coverage of SOI is that noone in the press factored out the architecture impact from the AMD vs Intel comparisons. Most press said AMD 90nm SOI parts have low power, Intel 90nm P4 parts have high power ---> SOI better than bulk Si for power (grunt, grunt, even a caveman can be an expert). They failed to effectively filter out the impact of the P4 design which was terrible for power and as we all know with it's long pipeline designed for clockspeed. You need look no further than the very good Pentium M (mobile) power levels on the same Intel 90nm process to see how poor the press understood the differences between process and architecture. (Not to mention the AMD droids who keep screaming SOI, SOI, yet another AMD innovation that Intel doesn't have!)
As you can now see with the advent of an architecture designed to be more efficient (Core2), the power levels between Intel and AMD are not that different DESPITE INTEL CONTINUING TO USE A "LEAKY"/"INFERIOR" BULK Si PROCESS.
Of course I'm unfairly not counting the offboard power from the Northbridge chip while AMD has this on the CPU. It however is wrong to simply add the Northbridge power to the CPU to estimate the power an Intel chip would have with an IMC and CSI as the Northbridge chips are one technology node behind and are not as efficient as it would be if it is on the CPU. You also can cut out the FSB portion of the current chips, and lower the cache amount which will partially offset the added power of "integrating a northbridge chip"
"Are you sure? If things are similar to 65nm then they should use 45nm just for lower power usage with higher clock speeds coming (much) later."
You're right - I keep forgetting the AMD Continuous transistor improvement process - the initial 45nm process will have similar transistor performance to 65nm but better thermals due to lower Vt's - so I imagine you will see a repeat of 90nm to 65nm transition. (I still think AMD will focus on server first though)
In theory AMD should be able to release the top bin on the new node right away but the fact that they didn't on 65nm tells you something. While AMD says "yields are mature", they mean yield in terms of working/not working chips. This by no means means that the PROCESS IS MATURE (meaning the clockspeed could be all over the place early on and they could be getting terrible binsplits on the high speed parts and be force to downgrade to lower bins).
This is yet another case where AMD is parsing their words carefully and as a result it is difficult to interpert what they say. Does anyone know what "asset light" is yet?
Oh I forgot they don't want to tip their hand to Intel - much like how they CHOSE not to release Barcy benchmarks not because they knew they would suck, but because they didn't want to give Intel a leg up on reacting to it!
Oh I forgot they don't want to tip their hand to Intel - much like how they CHOSE not to release Barcy benchmarks not because they knew they would suck, but because they didn't want to give Intel a leg up on reacting to it!
Good thing too since had they revealed it intel would have laughed at them and then closed down their R&D for a year.
Guru
As I see it, AMD is basic faced with the same problem they faced when scaling from 90nM to 65nM. As you elegantly explained, Intel has brilliantly found, Hafnium a nuclear control rod metal, (an excellent fast neutron moderator, by the way) was a solution in substantially reducing gate leakage. Hence, I’m guessing, Barcelona’s inability (presently) to deliver significant gains in clock speed will be exacerbated “exponentially” when scaled in an attempt to achieve 45nM production, let alone, the problems they are facing going to 65nM from 90nM. As you mentioned so many times before, you just don’t do a dumb shrink and expect miracles. This has now come to fruition, Kudos’.
Why on earth would anyone construct a semiconductor without doping the device completely? Can’t they afford the electric to get their ovens hot enough during the annealing process? (Sorry bad joke) I suppose there are advantages in reducing leakages in doing so.
No doubt, the transistor 'on state' specification and its hundreds of process variables are a key element, layer on layer, in producing faster chips. Obviously, time and money are needed to find the correct solution anywhere during the fabrication process. AMD has neither.
CTI while sounding nice to analysts, bankers, and Fanboys, seems like a very expensive proposition at 65nM and beyond. Sounds like a crap shoot and alchemy to me. “Let try a little salt while the pork chops are basting” And this, all the while, takes 16, very expensive, weeks between roasts!?!
Going to 45nM from 65nM at their present process many only compound their current problems with leakage and thermals, and perhaps, impossible with SOI, as proven with their 90nM to 65nM shrink. The size reduction here has, clearly, made maters worse, as you all predicted. Basically, one step forward, two steps back, at 45, two steps forward and three steps back.
So, while AMD’s tenacious and resourceful engineers are racking their brains trying to get SOI to work at 65, they will be pulling their hair out a 45.
Thanks for the insight. I will give your essay further study.
SPARKS
Why are you all talking about 45nm when there isn't any evidence that AMD has its Shanghai design taped out yet?
Maybe there will be something said about 'progress' next week when AMD posts earnings but right now all evidence posts at a 65nm process problem on the K10 design.
I mean, why would AMD 'extend' Brisbane (K8)?
AMD Emergency Lifeboat
The Barcelona dream is dead courtesy of AMD.
ROFLMAO
Sparks.
CTI offers one big advantage, and one that AMD needs more than Intel. CTI brings you process shrinks faster. So while you don't get device improvement right out of the gate, you do get the cost savings. And I think anyone that takes more than a cursory glance at AMD's balance sheet will agree they can use the cost savings.
CTI offers you the time value of money proposition in return for more design headaches down the road and the cost of constantly having your factory undergoing some degree of churn as you adjust the process to improve the transistors.
And in fairness to AMD, it isn't like they are blindly groping their way forward. Their partnership with IBM has already done the pathfinding. So the rocks in the road for AMD are finding manufacturable ways to implement the predetermined process changes.
Intel, on the other hand, pays for everything up front. By the time they move the process to HVM, it is cost effective and fully developed. Despite any claims Scientia may make to the contrary. The downside to Intel's approach is that you have to have the cash up front.
So as I see it you have one of two choices: One, pay for the process up front, which has a higher cost than just the development dollars, because of the cost savings you defer and the time value of money. Or, two, to do the shrink right away, get the immediate cost savings and deal with the rocks in the road while maintaining an HVM process. Neither option is perfect and I would propose that only the second choice is viable for AMD.
STOP THE CENSORSHIP
I'm a curious kind of guy and I wonder if we can put an end to Scientia's censorship. Based on comments that Scientia has made in the past, I believe that he places a fairly high value on the number of posts he gets on his blog.
Without the "Intel-lovers" (a nifty Abinstein euphemism for "fanboi") I think his blog would be next to dead. There is only so much self congratulation that those that buy all he says can heap on themselves. In short, he needs those of us who don't bleed green to make his blog work.
I'd like to test out my theory, but I can't do it on my own. I'd like to propose that all the "Intel-lovers" that are tired of the censorship boycott posting on his blog for 30 days. I wonder how many posts he will get then. Anyone up to give it a try?
"Hafnium a nuclear control rod metal, (an excellent fast neutron moderator, by the way) was a solution in substantially reducing gate leakage"
Actually, depositing HfO2 is fairly straightforward the real trick was/is the integration - specifically finding the right gate metals (that meet the gate requirements in terms of flat band voltages and also are compatible with the HfO2). Surface prep prior to HfO2 and etching of HfO2 are also not trivial issues either. You will see many companies with good capacitor level data (you don;t need a fully integrated process for this), but very few with transistor data near realistic process targets.
The CTI approach is not all that bad and has some advantages - if AMD waited for near final process performance prior to ramping they would fall even further behind Intel, and with this approach they can (theoretically at least) reap the economic benefits of the die size reductions (assuming of course yields and binsplits are reasonable).
The real problem comes into play when you enter VOLUME manufacturing (and I think this is what we are seeing on 65nm in general as well as Barcelona). The design and process are so interwined now that if you are constantly doing process steps via CTI this can magnify potentially new marginalities in the new rev. This means more development Silicon, more tapeouts and more iterative engineering or you have to leave products behind on older rev's (for example if AMD puts a new 65nm process rev in, do they bother re-qualing the K8 on it?).
This also means you have to choose between optimizing the design for the eventual future process rev or for the current one. If you design for the future rev, this may mean you take a short term hit on the current one (K8 65nm shrink?). If you optimize for the current process rev, the design may need to be re-worked for the next rev to take advantage of it.
Keeping in mind the bulk of the technology lifecyle is 2-3 years (there are obviously tails on the life cycle - think AMD 90nm right now, Intel chipsets, etc...), but is it really worth it to tweak a process multiple times during such a short time period. If you look at AMD's analyst foil graphs they proudly disply MANY CTI steps on each technology! (I'm not so sure this is a good thing) Intel does 95% of it's "tweaking" prior to ramp - yes this is seen as a brute force method but you then know the process will be stable for the next 2 years and the design team is working with a well known entity when doing shrinks or new products.
CTI is a classic example of the difference between Intel and AMD. AMD generally tends to favor the elegant and seemingly best engineering approach (HT/IMC, CTI, "native quad") while Intel prefers the simpler approach (FSB, MCM quad, finalize development prior to ramp).
Is FSB as advanced or well designed as HT? Probably not... is it needed or is there a dramatic impact caused by using this approach for 95% (everything but 4P+ server) of the products on the market today? No.
Is APM theoretically advanced? Maybe. But then again Intel designs a process to have as wide a process window as possible, so you don;t need to tweak it. Why would you want to live on the hairy edge in manufacturing? (I say maybe because I have yet to see a single piece of data to tell me what specific cost or technology advantage APM delivers - all companies use some sort of APM, I don't know enough about AMD's APM that makes it any better than TSMC, UMC, Intel, Renassas, etc).
Is SOI really needed? Intel gets as good or better performance without it and at a cheaper cost.
Intel is a manufacturing company that engineers with a manufacturable solution and will make the necessary tradeoffs prior to manufacturing. AMD appears to be an engineering company who first engineers a solution and then tries to figure out how to make it manufacturable and makes the tradeoffs in manufacturing (via delays, clockspeeds, yields binsplits, cost etc..)
"Going to 45nM from 65nM at their present process many only compound their current problems with leakage and thermals, and perhaps, impossible with SOI, as proven with their 90nM to 65nM shrink."
Well, leakage will get worse, but overall TDP will likely be better. TDP is off state + active power. Off state will get worse but active power will get better due to the Vt scaling (which means lower Vcore and therefore lower active power). The challenge may be on 32nm - and I think AMD has said they haven't made a decicion between SOI and bulk Si on this node. While 32nm seems a good bit into the future, Intel is already heavily into development of 32nm in D1d and most major process architecture decisions have been made.
“Why are you all talking about 45nm when there isn't any evidence that AMD has its Shanghai design taped out yet?”
Assuming your question is a rhetorical one, which doesn’t need to be answered, please, allow me to indulge.
First, from a business/investor perspective, this AMD/ATI/Barcelona scenario is a case study on a viable competitive company, making monumental errors in judgment in more places than I could possibly explain here. Let it be said, however, that this blogs history and chronology is a synopsis of those errors saved on the web for posterity. AMD fans no doubt would call us Intel Fanboys. This may be true, perhaps. However, as you go back and rediscover the timeline, most, if not all that was said and/or predicted here, came to fruition. It was almost clairvoyant the way the experienced, well educated industry insiders on this site read though all the nonsense with laser precision.
Contrarily, other sites, whose motive were/are suspect, were either misinformed, blind, or developed mentally disabled. That said, many investors who believed, and still believe, I might add, by some miracle, AMD could possibly pull this off in the eleventh hour. To their credit, in the past, AMD has.
Many who believed the spin have lost a great deal of money. We’re not just talking simple investors here; we’re also talking about huge companies/partners and billions of dollars in losses. This is an 18 month scenario that many have followed very closely.
There have been winners. Apple could have just as easily gone with AMD at the time. They didn’t, wisely. Sun, who was AMD only, made another wise decision. Cray and others were not so fortunate. They bet the farm, architecturally on Barcelona, as was pointed out to me by someone one this site. Cray Computer at this time might not be a wise investment. Apple would have been a brilliant move.
But, as we/I accumulate evidence to the contrary based on practical working experience of those on this site, we find, as you suggest, it would practically very difficult to do 45nM at all. It’s just another scene in AMD’s on going saga that is far more interesting than any TV show.
As for me, personally, as an Intel investor, I’ve turned 30% going with Intel at 18. As I gain an insight into the fabrication process and its variables, I become a more educated investor. From what I learned here, it keeps my position solvent and viable. Additionally, from all evidence, I plan to increase my earnings next year.
Read: Study the competition in every way possible, simple.
SPARKS
Actually, depositing HfO2 is fairly straightforward the real trick was/is the integration - specifically finding the right gate metals (that meet the gate requirements in terms of flat band voltages and also are compatible with the HfO2).
It is my understanding that the HfO2 is doped with some undisclosed element(s) as well. Doping is not technically difficult in and of itself and his been done in the industry for ages. But it does change the material properties (that is the point after all).
Changing the properties means that surface prep and etch characteristics are all dependent on the dopant(s) and their concentration. You can't just pull the HfO2 data out of a book and head off to the races. Just one more little wrinkle to contend with.
Pretty difficult without some specific inside knowledge. My guess would be future steppings will still be adding in some 65nm process improvements from AMD's CTI approach
-- OK -- I invite you to www.xcpus.com to have a discussion on this topic... you will find a definitive lack of fanboy posting, and good technical discussion.
I have never seen in the back-alley way internet discussion forums -- blog comment area or any public arena -- someone with this much insight.... it would be fun to have you there.
Now -- to everyone else reading these blog comments ... backtrack upwards and read what this person has posted. This is extraordinarily insightful.
As for SOI - the purported power consumption improvements is a terribly misunderstood and misreported fact. First off I think AMD is still using a partially depleted process on 65nm as opposed to a fully depleted process. An FD-SOI process allows for complete transistor (kind of) isolation and allows you to tailor other process steps better for power.
Ok, first BINGO, and yes AMD 65 nm is still PD-SOI. Second, on FD-SOI ... this is the holy grail of SOI processing, ultimately the Si over-layer will think up enough that by default, SOI will become FD more or less. At 65 nm, AMD/IBM are still PD-SOI, it will be interesting to see how much they scale at 45 nm, and if the Si layer is think enough to warrant pushing the active regions down to the Si/SiO2 interface.... ultimately it introduces several problems.
1) Subthreshold leakage ... (edit-- not whole quote, addressing your three
You have studied or you are in the industry. Yes, these are the 3 most important ones, various interactions can lead to exaggeration of one or another. However, with conventional SiO2, at 65 nm, gate leakage has overtaken subthreshold leakage as the predominant static power 'eater' so to speak. SOI addresses junction leakages, which is maybe, from various data I have been able to gather around the net and in the library, around 10%, sub Vt and gate leakage are the major bulk, which SOI does not directly address. It should be noted that part of the gate leakage does go through the junction, but it is a small part (you can apply Kirchoff's Law to a first approximation to estimate the portion of current pulled through the junction from the gate, it is not much).
The main problem with the press coverage of SOI is that no one in the press factored out the architecture impact from the AMD vs Intel comparisons. Most press said AMD 90nm SOI parts have low power, Intel 90nm P4 parts have high power ---> SOI better than bulk Si for power (grunt, grunt, even a caveman can be an expert). They failed to effectively filter out the impact of the P4 design which was terrible for power and as we all know with it's long pipeline designed for clockspeed.
Dman dude... here is a link:
http://www.matbe.com/articles/lire/298/pc-desktop-le-core-duo-face-a-la-concurrence/page21.php
It is too bad we did not get more data on clock for clock compare of Dothan/Banias on 90 nm because what you would ultimately conclude -- Intel's 90 nm process was more power efficient that AMD's 90 nm process at the time (not today, but at that time). AMD has parlayed a few clever tricks with 90 nm to squeeze out some lower power parts (EE editions), which include thickening up the gate ... (unofficial confirmation from semiconductor.com, so take this last part with a grain of salt).
Finally, I disagree with your assessment that there can be an improvement in the halo implant(well perhaps not disagree, but cautionary)... what I mean by this is that SOI inherently complicates implant, one of the major disadvantages of using SOI ... think about it a little... you have 2 to 10 MeV charged ions (some doubly or triply charged to increase energy) hurling into maybe 300-500 nm of Si, buffered by an electrical insulator, i.e. charging becomes a problem especially in spacially resolved impants (like halo), also diffusion becomes much more critical as lighter dopants (such as boron) tend to aggregate at the Si/SiO2 interface, creating charge traps... I have a few papers on this, and part of the reason I am suspicious that FD-SOI can be successful in a high volume situation.
Again @ the anonymous poster -- you are invited where the forum/response format is more amenable for a discussion. It would be fun. If you and I got into it, many people would have a great learning experience reading/following our debate.
Jack
"Actually, depositing HfO2 is fairly straightforward the real trick was/is the integration - specifically finding the right gate metals (that meet the gate requirements in terms of flat band voltages and also are compatible with the HfO2). Surface prep prior to HfO2 and etching of HfO2 are also not trivial issues either. You will see many companies with good capacitor level data (you don;t need a fully integrated process for this), but very few with transistor data near realistic process target"
There are three primary approaches to depositing HfO2 found in the literature and used in various types of integration schemes -- sputter deposition, CVD, and ALE (atomic layer epitaxy, sometimes called atomic layer deposition).
Of the three, ALE is by far and away the most controllable, and you are correct... depositing hafnium oxides, hafnium oxide silicates, or even zirconium oxides is trivial.
Jack
Jack
Don't you dare take away Guru!
SPARKS
I don't mean to take him away.... but comments in a blog are not as easy to have a discussion as a forum.
He can still post comments here :) ...
jack
Jack
See, here's the deal. We all knew Intel was using some exotic Hafnium alloy, and some esoteric (etching?) process to make it stick, and work; no doubt a very top secret and proprietary process. So much so, they are waltzing into 32nM! You guys confirmed it. This by my, albeit, limited understanding of the process, leads me conclude Intel’s mastery has increased its lead over any competition by a factor of two. Future financial gains are in order here! Without GURU this would not have been brought to light.
Hail GURU! $ Cha Ching $!
In the Know
“cash up front.”
NICE, got a ring to it. Cha Ching!
SPARKS
intheknow said:
I'd like to test out my theory, but I can't do it on my own. I'd like to propose that all the "Intel-lovers" that are tired of the censorship boycott posting on his blog for 30 days. I wonder how many posts he will get then. Anyone up to give it a try?
although i myself have stopped posting there, i believe it may be irrestible to some not to correct Scientia.
take for example:
Scientia said:
The two most significant developments (of 2007)have without doubt been SSE5 and motherboard buffered DIMM access..
very irresistable! that and the DTX claims... difficult.
roborat
"although i myself have stopped posting there, i believe it may be irrestible to some not to correct Scientia."
Exactly. I've thought about stopping posting there but it is so tempting to do it considering what people claim there.
Once he did ban me for some really weird reasons and then postcount dropped quite a bit. We shall see if it happens again.
I'll try to stay away from there for a while. After all I can always comment on Scientias blog here if I really want to :)
Intel to offer $35 -> $50 Dual Core CPUs!
http://www.xbitlabs.com/news/cpu/display/20071011171900.html
Interesting. I'd like to see how the performance goes having only 512KB of L2 cache vs. 1MB on the Pentium E CPUs.
Roborat, Ph.D said...
intheknow said:
...boycott ... Anyone up to give it a try?
although i myself have stopped posting there, i believe it may be irrestible to some not to correct Scientia.
take for example:
Scientia said:
The two most significant developments (of 2007)have without doubt been SSE5 and motherboard buffered DIMM access..
very irresistable! that and the DTX claims... difficult.
exactly. I have stopped to post there right after i notice biased censorship and one way name labelling.
it is quite tempted to comment on his biased post, but i managed to refrain myself doing that:) ... and I managed to use roborat's last post to do some comment ... :)
Nonetheless, both Sharikou and Scientia are quite successful in attracting viewer, one by stupid comments, BK prophecy and self advertising in other forum, and another one by biased comments yet proclaiming himself not biased and almost know everything, and censor facts that is against 'his facts'
take for example:
Scientia said:
The two most significant developments (of 2007)have without doubt been SSE5 and motherboard buffered DIMM access..
I never actually read the part about the two most significant developments of 2007 part of the article even though I read the article. Nice context. SSE5 and mbda significant developments of 2007. RIGHTTTTTTT
green glasses aside, I think ice cold 45nm is better.
Anonymous:
CTI is a classic example of the difference between Intel and AMD. AMD generally tends to favor the elegant and seemingly best engineering approach (HT/IMC, CTI, "native quad") while Intel prefers the simpler approach (FSB, MCM quad, finalize development prior to ramp).
I think that aside from the economic and production limitations, AMD takes these risks in order to differentiate themselves from Intel. It's a big risk because if you can't get the technologies working well enough (in terms of both performance and yield) then you wind up... well you wind up where AMD is now.
But the alternative would be to follow Intel's lead and let Intel dictate the technology roadmap without any attempt of your own to innovate or step forward. And if that's the case, AMD would have been behind Intel not just in ASPs and production, but in technology as well, guaranteed. And face it, if Intel and AMD were using the exact same technologies and the only difference was that Intel always had a X-month lead, why would anyone buy AMD?
(Well yeah, the situation right now doesn't seem much different, but that's because the risky path AMD took hasn't paid off as they hoped. But I think it was a worthwhile risk to take. Buying ATI, however, is something I'm not sure I understand.)
Of the three, ALE is by far and away the most controllable, and you are correct... depositing hafnium oxides, hafnium oxide silicates, or even zirconium oxides is trivial.
Okay, I know this wasn't meant this way, but it touches a nerve so...
{rant on}
There is nothing trivial about sustaining a modern semiconductor process.
As each node gets smaller, the need to improve defect performance increases. What was an inconsequential defect bin size in the last node may be critical in the next.
Keeping tools on target and running in the middle of the process window to produce the best speed bins requires constant intervention.
And then there's the bane of every process engineer's existence. Intermittent excursionary failure modes. I have spent months hunting for the source of some of these problems. They consume hundreds of man-hours and tool time. And in the end, you still live on pins and needles for a long time wondering if you really got it.
Finally, there are the problems that you may never find the resolution to, integrated issues (a problem that is caused by multiple tool interactions for those not in manufacturing). Hunting down these bugs requires a multi-disciplined team of tool experts, integrators and defect metrology working together to resolve the issue. Since resources aren't unlimited, working in one of these groups is just something extra that is put on the plate.
Add the fact that ALD is a fairly new tool set on top of this. Now you have all the above issues, but without the experience base of what the probable tool issues are and how to fix them. It will be years before ALD is a mature and well understood tool set.
So, no, I respectfully decline to accept the proposition that depositing any film on a semiconductor is trivial, even if the process of doing so isn't technically challenging.
{rant off}
I feel much better now. :)
Thank you all for your indulgence.
Sparks,
See, here's the deal. We all knew Intel was using some exotic Hafnium alloy, and some esoteric (etching?) process to make it stick, and work; no doubt a very top secret and proprietary process.
Yeah, people downplay the significance of the accomplishment in my opinion... Intel is indeed doing something funky and you can see it in how they are 'showing off' the concept. In all the high-k transistor pictures you never get to see the full transistor shot, only the 'zoom in' view of the gate stack -- you don't even get to see the top of the gate stack.... there is something going on that they, logically, are not sharing with the world.
The hodge-podge of different high-K candidates have been studied for 10+ years (about the same amount of time/focus SOI had before it went into volume production). However, the high-k integration is significantly more challenging than SOI, considering as you point out no only do you need to deposit the gunk, but you need some way to etch it controllably.
IBM has shown their high-k transistor, and just looking at the gate stack it is no where near the same as what Intel has put together... does this mean that it won't work?? No, not sure really -- IBM chose a buried metal/poly stack, Intel has gone for full replacement from what you can see in the TEM/SEM images... nonetheless, based on IBM issuing statements but Intel issuing demo's of working parts with launch in just a few weeks ... it suffices to say Intel is significantly ahead in this regard.
Jack
intheknow --
"Okay, I know this wasn't meant this way, but it touches a nerve so..."
Yeah, you misread -- it is trivial to deposit a film, such as HfO2 or ZrO2 ... trivial. Depositing a high quality film, patterning it if need be, etching it and adjusting processes to incorporate it into a working device over and over for thousands of wafers and hundreds of die on a wafer.... this is not something trivial.
Jack
Scientia really tries to make it hard for me
scientia
"However, the FP score is a problem since the FP pipeline for K10 should be nearly 100% faster"
I wonder why did he ever argue about SIMD when he doesn't have the slightest clue about it
"There are three primary approaches to depositing HfO2 found in the literature and used in various types of integration schemes -- sputter deposition, CVD, and ALE (atomic layer epitaxy, sometimes called atomic layer deposition)."
Yes there are three but realistically (at least for high performance applictaion), ALD is the only viable alternative.
Sputter is extremely difficult to put down that uniformly on say a 30A (or thinner) film. Also you cannot dope the film easily (you can do reactive sputtering but on films this thin it is a crapshoot).
CVD has similare issues but is more manageable. ALD is the best of all worlds - low dep temps, ability to control stoichometry on an atomic layer level and extremely uniform process. The major drawback is process throughput, but at films these thin that is not a big deal for a single pass critical process.
And yes I have both studied and have spent time in the industry - I post here because people seem to appreciate the comments and attempt to discuss them rationally (as opposed to the Scientia/Abinstein sites where they dismiss your comments if they don't agree with your point of view) - I will check out XCPU's though....
As for leakages, On 65nm I'm not sure if gate leakage has surpassed Isub or not (it's pretty close) on 90nm Isub was still in the lead - either way as you indicate they are oth far more important than junction leakage at this point in time.
"IBM chose a buried metal/poly stack, Intel has gone for full replacement from what you can see in the TEM/SEM images..."
Jack - It seems as though you have some background as well (some is a modest way of saying GOOD) The main potential issue with IBM's approach is thermal stability. With their stack it has to survive the subsequent anneal steps (especially the source/drain anneal which is north of 900C). At these temps you can get all sorts of issues - you can get mixing between layers (I assume IBM has put in appropriate barriers to avoid this), but you also have issues with many high K oxides crystallizing (you can probably find literature on this).
The high K's are generally put down amorphously - these are much better for leakage and other reasons. However when annealed above certain temps they have a tendency to recrystallize which may degrade performance (leakage, reliability and others...)
Of course the buried approach is cheaper (fewer processing steps) and if you can solve the issues specific to the high K gate stack the overall integration is also easier.
" intheknow said:
...boycott ... Anyone up to give it a try?"
I have posted there and at Abinsteins's site but their inability to even consider another side of the argument (even in the face of supporting data and links has lead me to no longer post at either site.
I do however like to still visit and derive the entertainment value of Scientia being a seeming expert among the clueless fans who never get exposed to the opposing (and often times correct) point of view. It is easy to appear to be an expert when you filter things that may expose some of his weak and unsupported statements.
It is funny to seepeople continue to attempt to "fight with him". At some point you have to wonder when are they going to say, "it just ain't worth it, the guy is ignorant (in the literal sense of the word) in many areas he comments on and has no interest in having a rationale discussion."
"Finally, I disagree with your assessment that there can be an improvement in the halo implant(well perhaps not disagree, but cautionary)... what I mean by this is that SOI inherently complicates implant, one of the major disadvantages of using SOI .."
You are correct - I was wrong here and should have left Halo's out. With a FD SOI solution you can play around with the well doping levels a bit more and use that to tune not only performance but also leakage. In an ideal FD (full depleted) device you should not even need Halos (though I'm not sure in reality if you could get rid of them)
BTW one of the main issues with going FDSOI is the cost of the substrate due to the technical requirements. With a FDSOI solution the active Si layer on top of the SOI is extremely thin and uniformity is EXTREMELY critical and difficult to achieve (I'm not if either a SIMOX or layer transfer process can achieve this if you are familar with SOI techniques). With a PDSOI solution the active layer is significantly thicker and a "couple of Angstroms" here and there won't mean as much to the uniformity.
I think this is why AMD is uncertain of SOI going forward beyond 45nm... (speculation on my part)
Please don't get my comments wrong, SOI is not a bad technology and has many potential useful applications. I'm just not sure how well suited it will be for high performance logic going forward.
For posterity, my comment on Scientia's latest blog entry where he's finally admitting that K10 isn't as fast as he expected:
I think we can safely assume that the new stepping supposedly used for Phenom will not show significant gains in IPC over the current Barcelona. The only tangible improvement will be from the use of unbuffered DDR2, and even that would be 5% at most. HT3: Absolutely no benefit to single socket performance.
So Scientia the next critical issue to tackle in order to get a true forecast for AMD's hopes of competing is all the roadmaps that VR-Zone has supposedly "confirmed" with AMD themselves:
1. Phenom X4 will not exceed 2.6 GHz until Q2 08. We already know that on the desktop, Phenom at 2.6 GHz is roughly equivalent to a 2.3 to 2.4 GHz Kentsfield. Hence, Phenom X4 is completely outgunned by Kentsfields in Q4 07 and Yorkfield in Q1 08 onwards, so Intel will reign uncontested in the high ASP quad-core desktop space.
2. Phenom X3 will not launch until March 2008. In addition, the same link shows that Phenom X2 (Kuma) will not launch until Q2 08. This means that Intel will effectively reign completely uncontested in the high volume dual-core $100 to ~$250 range for the next six months with Conroe and Wolfdale, especially as the mass rollout of Wolfdale in Q1 08 at these prices will push most Athlon 64 X2s into the sub $120 range.
3. Finally, rather than using valuable Fab 36 capacity to crank out dual-core K10 Kumas, AMD will be making faster K8 Brisbanes. The only logical explanation for this is that AMD cannot make fast K10s yet, even dual-core. There's a wall at around 2.6 GHz that they won't be able to really breach until at least Q2 08.
So the big question is, if these VR-Zone roadmaps are for real, does AMD have a prayer of surviving 2008?
P.S. The reason I hone in so much on AMD's finances in my comments is because most of the rosy outlook commentators on this blog seem to largely be blind to AMD's problems. AMD are only a couple quarters away from running out of cash at their current burn rate if they're unable to raise more capital.
“I think this is why AMD is uncertain of SOI going forward beyond 45nm... (speculation on my part)
Please don't get my comments wrong, SOI is not a bad technology and has many potential useful applications. I'm just not sure how well suited it will be for high performance logic going forward.”
Don’t underestimate the gravity of your comments. Obviously, as a highly training engineer you are cautionary and conservative, probably a requiem in the field.
However, rereading the entire comment piece again from start to finish, I printed it out for study for my 1 and ½ hour morning commute. Personally, I have come to the conclusion:
If SOI, with all of the above mentioned problematic issues, were such a good process, why is AMD still getting their teeth kicked in? ‘In The Knows’ comments, ‘JumpingJacks’ comments, and your comments combined as whole, dictate they went down the wrong road. Further, it will get worse as they get smaller. AMD can ill afford another Barcelona, Phenomenal tragedy at 45, if they ever get there. Christ, they haven’t resolved the issues at 65.
I will take your “speculation” as gospel before I even entertain the opinions of those Jackass pimps at Morgan Stanley and J.P. Morgan. They have agenda’s, you guys are simply brilliant, modest and unobtrusive. A very rare quality with Wall Street slugs who win going in or win coming out; THEY LOVE fluctuating prices. Think commissions. YOU are the technology encapsulated intrinsically, and on these pages.
Intel is a goddamned runaway freight train steaming away with absolutely flawless R+D, fabrication, implementation, execution, and manufacturing. Further, they’ve 10B in coal to keep the fires burning.
My extreme thanks to all for the invaluable insight into the industry, and for your personal time. Neither of which will ever go unappreciated or wasted.
SPARKS
"because most of the rosy outlook commentators on this blog seem to largely be blind to AMD's problems."
Axel, don't kid yourself, according to the in depth analysis above, AMD's problems are only exasorbated by their lack of "cash" for R+D. They are being crushed, literally, by Intel's execution.
Make no mistake, these well informed engineers are pointing the way to an extremely bad year for AMD in 2008.
There is absolutely nothing "rosy" on this page conserning AMD future prospects. At least none that I can see. We all understand they are not making money and are in extreme debt. This is a given.
SPARKS
Truely knowledgeable people have already figured that AMD's "100%" FP claim is based on cache performance, see. Assclowns with sensationalist blog titles will eat up anything AMD without a second thought to resorting to logic.
One additional thing to consider - one of Intel's public statements about SOI was that they though it's advantages grew smaller as the technology nodes progressed.
One of the reasons Intel did not go the SOI route (I believe) was that they had questions over its scalability. Intel will often pass on a technology if it is only useful for one or two technologies unless it is absolutely critical.
As one other commentor made a very good point that AMD as a smaller competitor to Intel may look to differentiate itself from Intel and hit the home run... either they didn't see the potential scaling issues or they thought they could overcome them in time? Either way it will be interesting to see what AMD does on the 32nm node. They have already swallowed their pride on the MCM approach, if the data on SOI does not look good they need to swallow their pride on that, too! (Also of note, SOI adds anywhere from 5-10% to finished wafer cost)
"your comments combined as whole, dictate they went down the wrong road"
At the time SOI may have seemed like the right decision - perhaps they did not have the data of how things would look at 65nm, 45nm, 32nm.... often these decisions have to be made with incomplete sets of data. I think in general Intel is more conservative and without clear data they will stay on their current course until there is compelling evidence it is not the right one. This is often a good thing in manufacturing, however you could argue maybe it was this same approach that kep Intel on the P4 architecture longer than they should have....
Please don't get my comments wrong, SOI is not a bad technology and has many potential useful applications. I'm just not sure how well suited it will be for high performance logic going forward.
Yeah, it is easy to get wrapped up in the SOI-rebuttle portion of the debate and push too far the other way... i.e. downplay the significance.
SOI brings many benefits -- but also introduces other complications that either fix the operational parameter space or must be process engineered around to avoid the pitfalls so to speak.
While I do not equate SOI to the magintude of the high-K implementation, that is not to say the ingenuity and engineering success to make it work was not stellar, it was...
What I think it boils down to is that the significance is as you say misunderstood and overrated. This is excusable to a large degree as many (most) people are not educated in device physics to understand all the implications.
Jack
One additional thing to consider - one of Intel's public statements about SOI was that they though it's advantages grew smaller as the technology nodes progressed.
Here is the paper Intel authored showing the scaling trends with feature size, and concluded that the benifits SOI may show over bulk dimished sizable as the device scaled -- this is of course for PD-SOI.
http://www.intel.com/technology/silicon/ieee/soi2000.pdf
Now, in hindsight, considering AMD's problems getting 65 nm clocks up to par, it tentatively appears Intel was right -- we will need to wait an see what becomes of 45 nm SOI devices to be certain.
On the flip side, Intel also was weighing in the return on investment is that 5-10% or so (which gets lower as you scale) worth the upfront expense if the application will only work over 1 or 2 nodes ... their conclusion was no. So, in my opinion, it was as much economical decision making as well as a technical one... there was simply no ROI for going SOI.
Jack
either they didn't see the potential scaling issues or they thought they could overcome them in time?
I think there is another factor in play here as well; IBM. I'd be very surprised to learn that IBM wasn't the senior partner in the IBM/AMD process development partnership.
And while IBM does world class research (perhaps the best), they have a history of not looking very far down the road. The move from the lab to the manufacturing floor has always been a tough one for IBM.
It is kind of the whole elegance versus expedience thing you were talking about earlier. Judging from the people I've known that work for IBM, they have a very academic, publish or perish, kind of mindset. Technical WOW counts for a lot in their culture. Unfortunately, WOW isn't always practical.
Axel, don't kid yourself, according to the in depth analysis above, AMD's problems are only exasorbated by their lack of "cash" for R+D. They are being crushed, literally, by Intel's execution.
Ya know, I've always thought that Hector Ruiz made a huge mistake when he issued the "dual-core challenge" to Intel.
I know it's tempting to taunt the big bully (which seems to be how AMD views Intel) when he seems to be down, but he never stays down. And when he gets up, he remembers.
I really think that Mr. Ruiz's stunt made things personal for Intel management. So in addition to the business need to get their act together, he gave Intel's management some additional incentive. I would say that hindsight bears out my initial impression that it just wasn't a good idea.
"Ya know, I've always thought that Hector Ruiz made a huge mistake when he issued the "dual-core challenge" to Intel."
There's that as well as the dual-core for dummies booklet stunt. I noticed AMD were particularly quiet during the IDF this Fall.. Perhaps they've finally realised that it behoves them to concentrate on their core strengths, rather than go for tacky publicity stunts all the time.
Intel could've done quad-core for dummies, or execution for dummies, or cache design for dummies, but instead we get things like "we think it advantageous to have all our cores working on our chips" when asked about the tri-core market, for example..
Totally different outlook. Design and execution first and foremost. With the elegant-design vs cost/time-to-market slider at the RIGHT point in the scale. This is something AMD has to work out - and fast. Where to find the balance between an elegant but expensive and difficult design to execute well vs expediency in getting product to market in a condition to take advantage of the demands of the consumers.
Talking of skulltrail, no doubt Intel is much better than AMD even when doing much worst products, that AMD already release 1 year ago...
Intel’s Dual-Processor Enthusiast Platform Set for Next Quarter Launch.
central processing units (CPUs) costing $3000
Sure why not AMD cost 300$ lets add a zero, zeros are cheap!
up to 128GB of PC2-6400 (800MHz) FB-DIMM memory.
Exactly what enthusiasts need, lots of slow RAM!
Intel virtualization technology and other capabilities
Yeah for playing virtual games you need virtualization technology!
And other capabilities such as heating your house while playing games!
the Skulltrail offers four PCI Express x16 slots for graphics cards to support 4-way CrossFire or SLI multi-GPU configurations
Direct copy of one of the most useless and inefficient AMD 4x4 features, Intel have to have that too!
The new extreme chips from Intel will have thermal design power of 150W
Don’t tell me that the 130W was not enough. Dammm another AMD lose, Intel have more CPU watts!
Intel Skulltrail gaming stations will easily pass $10 000 milestone
Shit AMD lost this round for sure. It's impossible to the 4x4 cost that much, Intel is the clear winner!
Intel guys are all dancing in the aisles!
Skulltrail is for bragging rights. The fastest gaming platform regardless of costs. Unlike AMD 4x4 that is slower than one Intel CPU.
AMD sticks it up the channel once again.
“Talking of skulltrail, no doubt Intel is much better than AMD even when doing much worst products,”
Well this is a good sign! The Fanboys are still reading! Perhaps, they can buy a clue, at least from a worst case, extremist position/point of view! Hang in there guy, even If some of us have difficulty deciphering your rant.
That said, I’m performance NUT and I find the ‘Skulltrail’ package a bit too rich even for my blood. I have as suggestion for you, however, as this package will be the extreme exception, not the rule. Look at the donut not the hole. We’re talking about 5 ton donut sitting in AMD’s lap. It’s the rest of Intel’s technology and volume production. It’s big, hard to swallow, and it ain’t gonna go away any time soon.
But then again, lurking in that active little mind, I suspect you already knew that. Things are gonna get “much worst” before they get better, trust me.
Oh, yeah by the way, the “dancing in the Isles” thing came from an excellent writer. Like him or not, he’s a good, stand up guy. He will wear a bunny suit (with EARS) for the world, and Paul Ottelini to see, when he’s wrong.
You pal, are no Charlie D.
SPARKS
( C.D. the beer invite in N.Y.C. is still open)
I have as suggestion for you, however, as this package will be the extreme exception, not the rule.
Funny that’s exactly what the AMD guys said about the 4x4.
Want me to post here all the junk the Intel fan boys wrote about the 4x4?
It applies perfectly to the Skulltrail.
You pal, are no Charlie D.
Geeee are you sure? I tough I was.
No one cares about 4x4 or skulltrail. They don't make a huge amount of money.
Yes we ripped it out of 4x4 but intel is only following suit.
Thing is 4x4 cost more than core2 and offered less performance. It was by no means the best money could buy.
Skulltrail will offer 5% more perf and cost 4x as much. If you wanna buy that shit then good for you.
Don't quote me on those numbers, they are just to illustrate my point.
Anonymous:
Talking of skulltrail, no doubt Intel is much better than AMD even when doing much worst products, that AMD already release 1 year ago...
I wouldn't say "worst [sic] products" as much as I would say that Intel manages to outdo AMD even with items that look like a bad or dumb idea. Granted, these products seem to be more of an idiot filter than anything else.
I think that for AMD, the 4x4 platform they offered was an attempt to generate some much needed sales and some buzz for their product after the success Intel enjoyed with Core2. Skulltrail just seems like Intel thumbing its nose at AMD, though I prefer that they had taken a more high-minded approach.
In any case, this looks like more a case of Intel puffing out its chest and strutting about, unlike AMD with the 4x4, which seemed more of a desperate act at the time.
Skulltrail is just a big ass "STFU " insurance policy against AMD.
If there's enough demand from Vodoo, Dell, and other boutique high-end gaming parties and they can make a tidy profit, why not?
"In any case, this looks like more a case of Intel puffing out its chest and strutting about, unlike AMD with the 4x4, which seemed more of a desperate act at the time."
Uhh...tri-core anyone? If AMD actually manages to sell some of these non-yielding quads, errr...I mean "native" tri-core, I'm afraid Intel might sell some tri's as well (though in Intel's case it will likely be a fused Nehalem good core to go from quad to tri). Of course AMD will have a 2 quarter lead in that all important tri-core market (that should get them back in the black!)
I though 4x4 was a waste, much like I think skulltrail is a waste (why not just go 2P workstation route? especially in Intel's case where you still have to go with the non-standard memory), but if there is a market for it...more power to both AMD and Intel. The thing I thought was wrong about 4x4 is that as much as AMD said it was NOT meant to compete with Intel's MCM quads it seems like that is what is what exactly trying to do, it also seemed rushed and things like power efficiency which AMD touts itself for, was poorly done. Then they said wait for K10, but of course the folks who are buying this and would want K10 would not want a rev-1 AM2 board which would not be capable of supporting the K10 unique features (HT3, split voltages) - AMD just seemed to be in constant spin mode on the whole 4x4 fiasco.
http://www.xbitlabs.com/news/cpu/display/20071012161815.html
Apparently, Intel feels it doesn’t need 1500 dollar CPU’s to eat AMD’s Pheromones for breakfast. Nor will Intel compensate with price drops for any lack of performance,if there is any.
It is abundantly clear, in the above road map, again, is another sweet spot similar to the Q6600 launch a few months back. The Q9450 will be another marketing/performance nightmare for AMD. This, I believe, is the one that targets AMD’s release and thereby setting AMD’s Pheromone launch price. (It will also lower the older Kentfield prices by default)
I can’t imagine the Q9450’s thermals and power consumption as the Q6600 runs incredibly cool. You can turn the Zalman LED 9700 to its slowest settings, barely a whisper! With the speed bump, Penryn core, and a faster FSB, the Q9450 is basically a Q6600 on steroids for 50 bucks more. Another one I‘ll buy, just for fun.
With all the delays, problematic issues, first tier OEM’s sucking up what ever AMD can successfully produce, and Channel partners gobbling the rest, I suspect the 3 Core losers are the ones the Fanboys will find available in volume. They give a new meaning to supporting the company, by purchasing AMD’s rejected quads, literally.
Can a new AMD 3 out perform an old INTC 4? Will the old 4 be cheaper than the new 3? We shall see.
Intel will not relent on its roadmap, product line up, marketing pressure, and execution. I have never said this before, but I now believe AMD IS truly finished. Wining in only 2% of the market (till 2Q 2008) will not save the company.
Then, there is Nehalem, primed and ready for HPC.
Everyone is corect above. This IS personal.
Tic Toc
SPARKS
I think tri-core would have to be a massive success for Intel to consider it. I think they'll have their "low" quad cores priced where AMD will place their tri-cores, and they'll just use the argument that asks why you'd want to pay X dollars for three cores when you can pay the same (or even less) for four? That and the constant insinuation that tri-cores are "broken" or "crippled" CPUs will probably make for a weak market for tri-core CPUs, IMO.
http://www.overclockers.com/
tips01230/
The often, and unwarranted, maligned Ed Stroligo over at Overclockers.com had an interesting piece for those of you, “In the Know”, might be interested in. It is precisely what GURU alluded to with his obvious conservative approach toward R+D, execution, and production. It seems, not only was Guru’s speculation on target, he hit a bull’s eye. (I told you his speculations were worth more than 100 IDIOT 'anal-ists’.)
Rather, complicated, for my lack of exposure in the industry, I will defer to the experts for their comment(s), if they so choose.
Humbly,
SPARKS
Sparks - interesting link (the one inside of the overlcockers article that is).
This is pretty much why you really don't want to do a CTI approach - the design and process development have become so interdependent that you can't easily change both variables and expect to have no issues. With Intel they have a stable process for 2 years and the design folk know what they are getting
The only problematic times are the intitial shrinks as they are coming out as the process is being developed, but at least here you have a known architecture to help minimize some of the potential issues. With CTI, AMD runs the risk of a new process-design interaction with every significant CTI change.
Obviously new architectures are not easy and can have delays - but those are issues driven by design and not process (as you have a stable process) - this makes troubleshooting and fixes usually a bit easier.
While CTI allows AMD to launch a new node earlier then otherwise they would be able to do, you have to wonder if it is worth it and if things will only get worse as the nodes get smaller. This by the way is also why I'm fairly certain that AMD will never do highK/metal gate on 45nm (well this and having some background on the integration complexity) - while AMD has previously held out hope that high K could be late 45nm or early 32nm the only 45nm would be development material in prep for 32nm (in my view). I think the late 45nm was purely PR puff to make folks think they are keeping up on the Si technology-side.
Sparks - while I appreciate the kind words, don't make me out for more than I am - anyone with reasonable experience and background in process development and manufacturing can see these things. I do smile when I hear folks like Scientia and Abinstein claiming all sorts of things when they have probably never even set foot in a cleanroom and seemingly have a purely book-read knowledge of the subject.
BTW - there has always been a battle between design engineers and process engineers. Design engineers, by nature, want every degree of freedom imagineable "just in case". Process engineers would want as little design variations as possible.
Back in the 0.18um and even the 130nm days, the process was still robust enough where it could handle much of what the design folks threw at it. This exploded as time went on and architectures became more advanced and soon design folks wanted everything - as an example one of the key variations in the metal CMP process is pattern density - you try to minimize dishing/erosion of metal lines (to both keep the resistance good and avoid non-uniformity issue which will be seen downstream). This is dictated by the density of metal you are polishing - you start polishing all metal and you then hit the oxide/metal patterns which allows you to stop the process (there are several techniques to do this).
Some design folks wanted the ability to do up to 90 or 95% metal density in certain areas! While I'm sure many of you are not CMP experts how do you expect the process to stop when you go from 100% metal to 95% metal? (It's nearly impossible to do this controllably)
So the design folks and process folks sat in a room. The process folks said if you want this absurdly high metal density you'll get X performance degradation, however if you cut the pattern density you'll get Y degradation. This allowed the design folks to decide which parameter was more important. It was a bit more sophisticated than that as a test wafer which had many pattern densities varying from 0% to 95% with all sort of lines/shapes/patterns was used during development to measure the tradeoff.
This sort of thing is done in nealy every major module in the fab now (and by all IC manufacturers). Doing this during the process development of a specific node is pretty bad - now imaging doing this during each CTI rev...and you have a manufacturing nightmare.
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