I thought I found Scientia’s title for his latest blog very appropriate, the "Eye of the Storm". This is usually used as a metaphor for a brief respite which normally leads to a false sense of security. I had an impression that he was trying to give an explanation about AMD’s current Barcelona problems but as it turns out, his explanation was even more chaotic than reality. The trouble with Scientia’s blog has always been his position in the Intel-AMD debate. And because of his desire to defend the indefensible, stretching the imagination in the style of Sharikou is becoming a necessity for him. Either that or he really doesn’t know what he’s talking about.
Take for instance when he wrote:
“…We know that AMD first demonstrated Barcelona November 30, 2006. This was presumably a stable Alpha chip. The earliest Conroe's were also Alpha chips and we know that it took Intel about six months to go through two revisions to get to the B1 release version. However, we also know that Intel's B1 had a minor bug that was fixed in the B2 revision, so B2 is also a reasonable assumption for production. We know too that the fastest that AMD could run off inline test chips would be 10 weeks. So, if we project this from the November 2006 demo we get:
November 30, 2006 – Stable Alpha silicon demo
February 8, 2007 – B0
April 19, 2007 – B1
June 28, 2007 – B2 (originally intended launch?)”
The alarming number of errors on this paragraph alone is giving me difficulty in trying to determine which one I want to start with. The most erroneous assumption Scientia made is his idea that silicon stepping is a standard measure that can be used as a benchmark. And what is even worse is he applied this benchmark to make a prediction for another company. What Scientia obviously doesn’t understand is that silicon stepping is a relative designation. It’s created for marketing with the purpose of creating distinctions between product/process revsions. A change in the letter signifies a major change while a change in the number is a minor change. B2 stepping doesn’t mean “launch ready”, it just means it had a minor change from B1 stepping. You have to go and read the documentation to understand specifically what was changed. It never is the same for any step for any product, let alone between Intel and AMD. To claim that Barcelona will launch at B2 just because Conroe did is the pinnacle of Scientia’s naivety.
And since we’ve established that the beginning of Scientia’s blog is grossly inaccurate I don’t see any reason to continue just to point out his mistakes. Besides, I’m not a fan of wearing down readers with lengthy posts.
-------------------
Update1: AMD’s Presence in Workstations Plummets in Q1’07 - John Peddie Research
Vendor - Q2CY06 --- Q4CY06 - Q1CY07
Xeon ----- 86.7% ------ 88.9% ---- 92.0%
Opteron --- 3.3% ------ 11.1% ----- 8.0%
It looks like Intel made a brilliant move to offer Quad-core conquering the workstation segment while the competition is struggling to keep up. Once again it shows how time-to-market is key.
6.13.2007
Eye of the Storm Explanation Indeed
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26 comments:
Wow - his lack of understanding is really scary. I wonder how many people will read that and think wow he really knows his stuff....
Here's a couple more errors (we shoud start a tally):
2.5 months to move production lots through a fab? Maybe in the good ole 180nm days. He says 2.5 months for a new stepping - these are priority lots which are hot boxed and moved throgh the fab quickly (to get max information turns).
You can't do this with EVERY production lot - try 3-3.5 months and oh hey, we should probably test and package these chips to before the go out to customers, no?
"If you launch a product with nothing but ES samples then that is a paper launch. This is pretty much what Intel did when it previewed Conroe six months before availability and what it has repeated with Penryn."
Apparently Dementia is condfusing launch with "demo" Intel demo'd Conroe on ES's in March, but that wasn't a launch - they weren't advertising product was available in March?
And Penryn? Did Intel launch Penryn without me knowing? Dammit, you guys have to keep me up to speed - where can I buy those ES's that Dementia is talking about. Here I was thinking Penryn was going to launch in late Q3 or Q4 and appaarently it's alreadt been launched on ES samples!!!
Part 2:
"Back in January, Randy Allen at AMD stated that K10 would be 40% faster than Intel's best Clovertown. And, presumably this would be with the 2.5Ghz speed K10. At the time that Allen said this, Clovertown was only projected to clock to 2.66Ghz. K10"
Umm.. I think it was known Intel would have a 3.0GHz part (Apple part anyone?). Also I PRESUME when Randy Allen said Barcelona would be 40% better than Intel's "top " part I PRESUME he means whatever AMD's top part at the time of launch is will be 40% better than Intel's top part...
"Of course, I've also seen lots of people trying to pull some kind of estimate of performance out of the two benchmarks that have been done. The problem is that A1 silicon is usually bogged down by patches and won't really show performance."
Hmmm... here I was thinking at least one of these demos was based on B0 stepping at Computex. Wasn't A0 the infamous "task manager" demo - oooh look all cores are loaded! (of course as postulated by some, this was because the chip sucked so bad it was running a ridiculously low clockspeed and was 100% taxed due to AMD moving the mouse across the screen!)
"This year, it looks like AMD is pushing the meeting back one and a half months and “will hold its 2007 Technology Analyst Day on Thursday July 26th, 2007”. The push to a later date probably has to do with the fact that DTX and mini-DTX motherboards are due in August as much as the time frame for K10"
Yeah - AMD pushed back the Wall St analyst meeting for DTX, right, because showing that off to Wall Street will clearly show them a huge benefit coming to AMD down the pipe and a clear turnaround in financials. Nothing to do with Barcelona, that's really not that critical to talk to analysts about - that's only going to be our high end, high margin server parts and hopefully allow us to recapture / stop the bleeding in the higher end desktop market. No ,DTX is far more critical to the analysts - better push back the meeting so we can show them the goods! Are you freakin kidding me?!?!
"July also makes sense because FAB 30 should be into the 300mm conversion and FAB 36 should be working on 45nm, and AMD will surely want to mention them."
Uhh... no... Amd just starts to bring down 200mm capacity in Q3. Actual 300mm capacity doesn't come on line (in terms of outs) until Q1'08. Yeah let's show the analysts how we rip out some 200mm tooling? Barcelona? Bah - come see us take out some 200mm equipment. And 45nm - they showed a meaningless wafer already (and claim it's working), what are they going to be able to show in terms of 45nm in July vs in June?
Scientia: Finally, even with low yields, AMD could produce enough K10's to cover the server segment where volumes are low and margins are much better than on the desktop as they did with K8.
is he talking about shipping bad parts that can only perform equally against K8? Is he talking about AMD taking away market share from itself while AMD further humiliates itself and destroy the Barcebologna reputation with crappy parts? Wow this guy really is clueless...
Part 3 (and then I promise I'll stop for a while)
"AMD would probably also release a quad FX version since these platforms could handle more heat and power draw. With its enhanced SSE performance there is no doubt that even a lower clocked K10 would add value to the current offerings." (This is what would AMD if K10's issue is that it is running hot...)
Hmmm... what was the clock speed of FX again? (those are high end parts no?) So AMD would take a part with heat issues and put it into ther highend, highest power segment because the heat issue would be least seen here? anyone else find this strange. If the part were having heat problems - I don;t thik trying to launch you r highest speed segment is the place (Sempron/low end anyone?)
"A patch that did not degrade performance would not cause a delay. A serious design flaw would likewise not cause a delay. Process or yield problems would only cause the initial clock speeds to be lower rather than causing a launch delay."
Ok, I'm with him on the first statement. But a serious design flaw would not cause a delay? Huh? Basically AMD will just ship out/launch crap, if it requires significant time to fix it? How exactly would yield problems cause clock speeds to be lower (does he mean bin splits?) . Yield problem mean die not working, grunt, grunt....
"was a bit surprised when some suggested that the lack of an elaborate showing by AMD at Computex meant something. However, if you look at the 2006 Computex, AMD showed almost nothing beyond AM2 systems and motherboards, and AM2 had been officially released a month earlier."
Yup - he nailed this analogy. Let's compare a socket change (and IMC change) with a brand new architecture change.
I mean if you're not going to go full bore and show off a change from DDR to DDR2 which showed no performance advantage at the time, why would you show off an architecture change that will beat Intel by 40%!
At what point did Dementia, crap I mean Scientia, become an apologist/excuse monger for AMD?
The reasons for pushing back analyst day (for every reason BUT Barcelona readiness) is just classic! That is bordering on Sharikou level! Maybe they'll give each analyst a DTX board, a used piece of 200mm equipment from the fab conversion they'll be showing off, and just sit back and watch that old stock price take off! They'll be lighting cigars with $100 bills that they suckered all those convertible bond investors into! Oh you wanted us to use that money for expansion and business expenses?
Wasn't Penryn benched on Ax?
27.93% decrease, tsk tsk.
Well, at least I can give you, roborat, and your posters credit for creativity if not accuracy.
For example, I never said that B2 meant production ready; that is a red herring of yours. In reality, you can get lucky and have a good chip with first silicon or it can take you seven or eight (or more) tries. B2 was simply an estimate that you readily misinterpreted as a hard release point and then you went on to ignore where I said that the B2 stepping may not be production ready. For that matter, the B3 may not be production ready. The truth is that it could indeed take AMD until 2008 to deliver a working chip; you really should pay attention to what I write instead of making up things.
Nor did I claim that samples were delivered to customers every 10 weeks. This is simply the fastest possible pace that AMD could make changes to correct bugs in K10. In other words, if the current version is not ready then you can't have a fixed version for at least 10 weeks. It takes longer than 10 weeks for a chip to actually go from start to channel. And, even at that point you only get a trickle as the first chips come off the line. It takes at least a month after that to get any volume out.
Your misinterpretation about major design flaws not causing a delay is also typical of what I see here. Why is it so difficult for you to understand that you can't fix a major design flaw by pushing by production by 3 or 6 months? You only have two choices: you either go ahead and produce the chip or you wait a year (or more) until you have a fix. Obviously the K10 chips run since there have been demos. As long as they can outperform K8 chips at the same speed they would still have value even if they don't reach their intended speed. Again, this is what Intel did when it released Williamette.
Your statements about the Analyst Day pushback are also classic misdirection. I can't believe you are crazy enough to think that the date was related to K10 delays. That meeting has been scheduled for quite some time and it would have been impossible for AMD to know that far back how long it would take for K10 to be released. What makes your argument so absurd is that AMD may not even have a production ready version in hand by the time of the meeting. And, without a production ready chip they would still be unable to give firm release dates. Are you so delusional that you think AMD will just keep pushing the meeting back until K10 is ready?
On the other hand, AMD does know when DTX and mini-DTX motherboards will be ready. These are a lot more significant for about the lower 2/3rds of the desktop market (everything below ATX motherboard size) than you admit. Even today, Intel has nothing at all competitive with mini-DTX. Is this a high margin market? Of course not. But in terms of maintaining desktop share, it is important.
If you had remembered some of my past comments I compared this to the situation in 2002 when AMD's K7's were being pitted against Intel's Celerons. Naturally, it was no contest for K7 and this allowed AMD to hold onto the lower desktop range. This situation is similar with mini-DTX having considerably more value than Intel's mini-ITX offerings.
See this Randy Allen video:-
http://virtualexperience.amd.com/index.html?cid=quadcore&co=quadcore
Barcelona will frag Clovertown by 40%.
Intel BK 2Q08.
Scientia said:
"I've seen commentors on my blog and web authors (who should know better) claim that silence by AMD on these matters will erode confidence and hurt AMD's sales. These people tend to forget that the tiny percentage (less than 0.1%) of enthusiasts who really care about top performance are only a tiny fraction of sales."
I think you misunderstand. I agree that a lack of confidence amongst techies and hobbyists is not a big deal. Not only are they a small percentage of the buying market, they are also very fickle.
The concern is that there will be a loss of confidence amongst OEMs like Dell and Gateway. They're not going to take a chance on placing substantial orders until they see that AMD is able to not only produce Barcelona in quantity, but also at speeds that make it competitive.
You are correct: the average buyer doesn't know or care about chip design and delivery schedules. But he won't be buying an AMD system if OEMs aren't offering them. That is why there is concern if there are delays or problems with Barcelona.
B2 was simply an estimate
Arbitrarily unsubstantiated chosen number.
As long as they can outperform K8 chips at the same speed they would still have value even if they don't reach their intended speed.
Good idea, AMD should release 1.6GHz quads faster than 1.6GHz duals, that should really challenge Clovertown, or even their current 3GHz dual cores.
hat meeting has been scheduled for quite some time and it would have been impossible for AMD to know that far back how long it would take for K10 to be released.
They've only said middle of 2007 for so long *whistle* Is it now middle of 2008?
"Nor did I claim that samples were delivered to customers every 10 weeks. This is simply the fastest possible pace that AMD could make changes to correct bugs in K10."
Scientia - you really have no clue/background on chip development (on the process/fab side) do you?
So let's walk this through for you - a rev is tested (let's call it B0 for kicks). AMD finds a problem and determines they need a new stepping and so they put more wafers into the fab and ~10 weeks later initial wafers on a new B1 stepping come out? (Again you are assuming this is initial wafers but this is a fair estimate as these will likely be priority lots)...
A seemingly simple theory...but there are a few holes in it....
When the B0 rev is tested and found to have a problem, it actually may take some time to IDENTIFY the problem... Once the problem has been identified a new design solution has to be developed to address it (Maybe I should say tweak, as I;m not trying to imply a complete re-design)- I hear this may also take some time....
Now of course you probably want to at least model the solution before you go off and spend MILLIONS of dollars on a new mask(s), so this takes a bit of time too....
So now you are ready for a new stepping right, let's get those wafer moving boys!
Well not so fast - a new stepping is a NEW MASK, masks take some time to generate. The OPC algorithms (that's optical proximity correction - which takes the shape the designer wants to draw and turns it into a mask pattern that litho will be able to print to that shape) are so complex that they can take as much as a week just to convert the a single mask design drawing into the corresponding mask design.
Of course, now you have to make the mask....
So while it may take 10 weeks best case to move wafers through a fab you have omitted all the work need prior to starting the wafer.
So now you are saying how is it theatsteppings seem to come out in intervals of 10 weeks - clearly I have made some mistake because the data say there are stepping out in 10 weeks!
Hmmmm....tough one...Early in the development you could be doing parallel steppings and testing multiple things in parallel - this can be done on early steppings as there are mutliple problems that need to be tested and validated. Rather than a single serial approach, early on you will do a parallel approach with multiple fixes (and is some case you may need to test parallel solutions to a single problem if you aren;t sure of the solution) Crudely, this is like a main SW revision with mulitple branches of patches being tested on simulatnetously.... of course in the end you have to combine everything together and do more regression testing to ensure new fixes don't have some strange interaction.
Soo as you get to the final stepping, or near the final stepping, you have to wait and do it serially. This is also not like SW where the code can be just combined quickly together - the multiple stepping fixes you were running in parallel may now require new mask(s) to combne them together. So as you get closer to the final stepping it will no longer be on this ideal 10 week revision timing..
For the advanced folks - most IC manufacturers to reduce the waiting time impact for new masks will stage priority lots at different points in the process flow while waiting for a new stepping (or convert a normal paced lot that is in the neighborhood of that step into a priority lot). If you are waiting on a new stepping for say metal 1, there is plenty of wafer processing that can be done in parallel with the mask being developed. Of course it all depends on where the issue with the new stepping is - if it is early in the flow (say STI, or an early implant step), this doesn't cut much time, but if the issue is later in the flow (say one of the upper metal layers) it will cut substantial time.
Of course what do I know, my knowledge comes from actually working in and around a fab... Just ignore what I said above and defer to Scientia's vast expertise on manufacturing, steppings, and design...
Scientia's manufacturing expertise is composed of Powerpoints on APM lol.
I think I just realized how Scientias articles work... He takes an external observation (like Intel had new steppings coming out at ~10week intervals) and then fits his own model to that (not knowing the why part), so he can then extrapolate the future (or performance).
The only problem is to generate a model you need an understanding of what is going on - it is very difficult to just make up a model just from empirical observations.
So let's look at steppings... ahhh... I see steppings coming out at 10 week intervals - therefore it must take 10 weeks for an aggressive timeline for a stepping (now does he understand what is going on behind the scenes? Has he considered the steppings while #'d sequentially, may not be running SERIALLY?)
So AMD need X # of stepping and each stepping takes Y weeks so launch is in X*Y weeks... easy model! of course the # of steppings left to do is based on an arbitrary stepping name convention and the assumption that Intel uses a similar naming convention to AMD...
Classic example #2:
- Via market share down ~3% in one quarter
- Intel market share up ~1%
- AMD market share up 2%
Conclusion - obviously AMD is eating into Intel's market share (since that was what was happening in the past) and Intel just ate Via's share to offset the losses to AMD?
Again easy, simple, model and conclusion, easy for people to follow, easy for the fanboys to accept... but based on no data whatsoever... of course it could have been AMD taking Via's 3% market share and Intel eating into AMD's market share at the same time, or Via's share could have been split between Intel and AMD... but hey why consider those scenarios?
Now fast forward 2 quarters; AMD is losing share and it is (in my opinion) probably that Intel was eating into AMD's upper market share (as this was in early Core 2 days) and actually AMD offsetting it by eating up Via's... of course I also have incomplete data on this so that's why I'm stating OPINION as opposed to making a CONCLUSION.
Again with incomplete data and a lack of uderstanding of the fundamentals that go into that data, it is really hard to draw conclusions and build projections based on (limited) empirical data only.
"I've seen commentors on my blog and web authors (who should know better) claim that silence by AMD on these matters will erode confidence and hurt AMD's sales. These people tend to forget that the tiny percentage (less than 0.1%) of enthusiasts who really care about top performance are only a tiny fraction of sales."
Forgive me, but I think you all underestimate the net effect of the top ‘whatever’ percent crème de la crème.
First, this is the percentage Intel gives away to no one. This is the percentage they took back from AMD. This is a lock. This is the top dog, fear factor. Call it the undeniable edge, marketing coupe.
Secondly, the “trickle effect” the highest performance chips and architecture trickle down to the ‘lower performance’ parts. Basically this sets the benchmark to which everything else down the lineup is compared, and/or priced. This sets up higher sales in the lower priced segment by default. As new scaling and architecture comes in, those ‘older chips’ get cheaper. C2D will completely dominate the lower sector when the prices drop as 45nM ramps. (As if they don’t already?)
Third, with such a radical shift in architecture so quickly, in conjunction with such a dynamic performance lead within 12 months, it is now a mater of how long, not if, Intel can sustain such a lead. You all KNOW better than I, Intel is pushing the design/architecture/power/manufacturing envelope during the next 2 years.
Fourth, and finally, Intel has nothing to lose. They are hell bent on regaining lost market share; crush any competition, extinguishing any doubt, regardless of the cost. They have 10 billion in cash and have 4 new Fabs to do it, with another going up in China.
No one is going to skywrite Intel’s company picnics again. This is the 0.1 percent solution, not the problem, which 'only techies and enthusiasts care about.' At this juncture, Barcelona is becoming less significant as each DAY passes.
Sparks
https://www.blogger.com/comment.g?blogID=2602471396566186819&postID=5282071734927150562
"We don't launch until our customers are ready to go with products that are using our chips," says spokesman Phil Hughes."
How's this for interesting double speak from an AMD spokesmen - read it carefully - he said they don't launch until their customers are ready, but he conveniently omits stating that if the customers are ready, AMD will be ready.
Obviously it makes no sense to launch a product if your customers are not ready for it - but that doesn't necessarily mean the product is on time/ready.
Overall it is an interesting article - it wonders if Intel's price cuts could be due to Intel anticipating Barcy taking the lead.
However there is one fatal flaw in the author's theory... If Intel were worried about K10 performance overtaking them in Aug and trying to preempt with a July price cut why would Intel cut BOTH server and desktop when the only chips AMD are launching initially are server chips? Why wouldn't Intel just cut server and follow-up with desktop cuts at a later date when AMD readies their K10 launch?
The fact that they are doing both at the same time suggest that it is more than just pre-emprong K10. Maybe starting to clear inventory in advance of Penryn - although that is still a bit out... Maybe it's just a normal price cut (I think Intel usually does this twice a year and this would be the 2nd major one this year). Maybe they are making way for a new top bin SKU? Maybe Intel is just trying to take back more market share?
Or entering the Scientia zone... maybe they are trying to steal the thunder away from AMD's analyst day? or DTX? On the other hand, maybe another reason for AMD moving analyst day was to take press away from Intel's price cuts? (I'm joking folks!)
"If you launch a product with nothing but ES samples then that is a paper launch. This is pretty much what Intel did when it previewed Conroe six months before availability and what it has repeated with Penryn."
Apparently Dementia is condfusing launch with "demo" Intel demo'd Conroe on ES's in March, but that wasn't a launch - they weren't advertising product was available in March?
apparently he is not confusing, but acted as AMD fanbois, claiming Intel's demo 6 months before launch as paper-launch, and AMD's task-manager demo more than 6 months before launch as a good sign of a working chip ... you get the point now? :)
Scientia said: "I never said that B2 meant production ready"
Earlier scientia said: "
...so B2 is also a reasonable assumption for production..."
... right.
pointer said: "apparently he is not confusing, but acted as AMD fanbois, claiming Intel's demo 6 months before launch as paper-launch, and AMD's task-manager demo more than 6 months before launch as a good sign of a working chip ... you get the point now? :)
good point!
I have to be honest, this is one of his most erroneous posts. As you read through his blog, you make a short list of things you want to refute. The problem is by the time you reach half way, you already have a grocery list. And even before you reach the conclusion, you find yourself so worn down and just couldn't be bother.
I refuted his first point and that was it, i felt it wasn't worth it to educate him. I'm grateful a lot of posters did continue what I started. Thx all.
"apparently he is not confusing, but acted as AMD fanbois, claiming Intel's demo 6 months before launch as paper-launch, and AMD's task-manager demo more than 6 months before launch as a good sign of a working chip ... you get the point now? :) "
Thanking you for enlightening me! I still have much to learn in the ways of understanding Scientia /AMD-fanboy speak master!
For another good laugh go over to Abinstein's blog and check out his "education" people in the ways of WID and yield! If you have a semiconductor background it's a pretty good chuckle! The best part is he doesn't even understand how wrong he is (or is in denial) and continues to try to argue his way out of absurd statements by making even more absurd statements, at the same time telling people that they don't realize how wrong they are!
For some reason the link is on the main page, I can only think it is there for comic relief.
Roborat, Ph. D. said...
Scientia said: "I never said that B2 meant production ready"
Earlier scientia said: "
...so B2 is also a reasonable assumption for production..."
... right.
14 June 2007 21:48
Classic.
Just when you think Scientia can't get any lower, he manages to drain a little more out of the pool:
"Intel's surprise was K7's ability to clock, partly due to AMD's more advanced copper process." One of Scientia's latest comments in the Eye of the storm "article" (and I use the word article liberally)
Hmmm... If Scientia even had a basic process understanding he would realize in the days of k7 clockspeed was governed by the front end speed (transistor switching) which has nothing to do with the implementation on backend Cu metallization.
It is important to continue to scale the backend so RC delay doesn't becomme the limiting factor (which is what Cu and continued work on low K ILD's does), but Cu is not responsible for higher clockspeed ESPECIALLY in the days of K7 where the process technology was dominated by transistor switching speed.
It is extremely frustrating to hear people like Scientia and the newest AMD apologist, Abinstein, throw around process technology on their blogs and in their comments, without having a freakin clue...
http://www.theinquirer.net/default.aspx?article=40363
Surprise surprise, a whole year behind.
A claim of authority by someone so ashamed of his comments that he has to remain anonymous carries very little weight with me.
And, I suppose if someone is unable to write anything of their own then critiquing mine gives them something to write about. This probably also gives Intel employees a place to vent. Have fun.
"A claim of authority by someone so ashamed of his comments that he has to remain anonymous carries very little weight with me."
Take note of the Shari-kook approach, if someone makes some valid points attack the poster and try to distract people from the validity of the points...
Classic Scientia: "If you are looking into the future and talking about 45nm then what about early 2009? With both AMD and Intel on 300mm wafers and 45nm processes and Intel moving to native quad Nehalem won't Intel lose their wafer, process, and MCM cost advantages?"
WOW! This isn't just bad, it is ridiculous....
Intel will be ~90% 45nm by early 2009 (crossover on 45nm will be in Q3'08 according to Intel). So this will represent no cost advantage over AMD which is STARTING their 45nm process in H2'08... What % of AMD production will be 45nm in early 2009? Might the mix of 65nm and 45nm parts lead to a "slight" (some may say substantial) aggregate cost difference and advantage for Intel? (Just a crazy thought on my part!)
MCM advantage gone with quad...hmmm...would Intel consider, I don't know, an 8 core MCM by putting 2 native quad cores together... I know this is a HUGE reach on my part as when Intel moved from an MCM dual core to a native dual core they gave up on the MCM approach.....
....for about 6 MONTHS,until they released an MCM quad! But hey I think we should assume Intel will abandon this approach especially considering how unsuccessful it has been proven to be - Intel is having a heck of a hard time moving those MCM quad's as they are non-native!
Process advantage gone in 2009? Yeah, I'm pretty sure when AMD's VP of Technology and Manufacturing said they will not be implementing high K / metal gate until late 45nm node or 32nm, he must mean ~6 months after AMD starts the 45nm ramp. Don't assume PRINTING 45nm features means you will have equivalent 45nm performance - there is more to technology node scaling than lithography and feature size. If I read your comments, you are indicating that 6 months after AMD starts up 45nm they will be at same 45nm technical performance level as Intel's 45nm?.
Considering how AMD touts their CTI transistor approach and how using the previous generations transistors to start the next technology node up, it is a huge stretch to assume techincal performance will be on par. Look at what Intel's clock speeds are on the shrink of a processor at the start of a technology node, and then look at AMD's (65nm Athlons, being a good example).
I'm sure AMD's 45nm process will eventually catch up (or get close) but don't assume when AMD starts their node, the technical performance will be on par with Intel at the time they started their technology node.
Now this being an anonymous comment, you can just choose to attack me if it makes you feel better, but it won't change the facts above...Have a nice day!
It's just as well you stay on your own blog where you hope people just take whatever you say as gospel and don't challenge some of your ridiculous claims.
Once again, Scientia being superior, because he blogs (oh, "writes something of his own"), attaches the scifi accident pseudoname to himself instead of a real name, belting out how he doesn't give any thought to anononnimmies for what, the 5th time now?
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