How do you protect your margins from commoditization? Sell to an OEM with a proprietary product. The Apple-Intel alliance is hitting it big with healthy sequential growth rates both on the mobile and desktop segment. The money Intel makes selling to Apple is shielded from the protracted price war with AMD and should be a very useful leverage.
Macworld reports:
The May boost put Apple's laptops in fourth place, behind Hewlett Packard, Toshiba, and Gateway said Baker, and moved its combined laptop-desktop sales share from 11.6% in April to 13% last month. Separately Apple notebook sales rose to 14.3% of overall purchases from 12.5%, while desktop sales increased to 10.4% from 10.2%. In retail only, sales Apple showed a slightly smaller increase, from 9.6% to 10.8%.
6.25.2007
Apple Gains Notebook Share
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9 comments:
Scientia showing his (lack of) expertise in the Si processing area (AGAIN):
"Also, I've already seen the particle defect rate for AMD's 45nm immersion process and it is doing well."
He's talking about the particle rate on immersion vs dry litho - of course the OVERALL process yield is just a bit more significant than just that! (He's looking at 4 out of several hundred process steps, while also ignoring that smaller defects which might not have been a problem on 65nm might actually be a problem on a smaller node side - so equivalent defects is not actually the whole story). Perhaps he thinks that is the only change from 65nm to 45. Perhaps he thinks you get transistor speed from just making Lg smaller... (Or perhaps he doesn't have a clue, has found a single data point which actually would not be predictive of yield and is trying to confuse the masses?)
The other funny part is that he equates simple particle density to yield, there are NUMEROUS sources of yield issues outside of particles and short of AMD sneezing on the wafer he is missing the boat...
"If AMD follows pattern they will shrink the process a second time maybe Q4 07."
Shrink the PROCESS? WTF?!?! Shrink it from what to what? AMD may optimize the DESIGN and chip layouts better for 65nm and shrink products but they don't SHRINK the process a 2nd time (unless he's confusing speeding up transistor performance with SHRINKING the process). What is AMD running a 75nm process now? Or are they at 65nm and shrinking it to 60 or 55nm? Shrinking should not be confused with CTI or re-optiomiZing a chip layout. (this is not "shrinking the process")
"We can tell that things were not exactly up to speed with Brisbane because the die shrink was not that great on 65nm."
So the amount of die size reduction is proportional to increased speed? I guess in simplified Dementia world that is the case - the speed that AMD didn't get on 65nm was not because of the amount of "SHRINK", it was because the initial 65nm transistors were essentially glorified 90nm ones with smaller gate size (and Vt's). This is what Scientia has failed to understand all along when he compares how far behind AMD is with Intel on process technology. The 65nm process at ramp, didn't have many of the technology improvements, AMD was essentially (to dumb it down) printing 90nm transistors with 65nm features (In reality this is not quite true as they also retargetted Vt which is what gave the power improvements). However a lot of the changes to improve transistor
(strain, not sure about salicide) were yet to be implemented - this is far different from Intel which at technology node ramp has more or less gotten the final transistor performance (while they will tweak over the course of the node, they generally target a >30% improvement over the previous generation). This is why Intel is much farther ahead than AMD claims or it appears to the lay person. For AMD to catch up on things other than simple FEATURE printing they need more time into the ramp.
While AMD EVENTUALLY does the same they do not get there until much later in the node lifetime. So when he says "look AMD's only a year behind as they had 65nm products 1 year after Intel" or it will be 6 months on 45nm (through some complete lack of basic calendar skills), he is only compering SCHEDULE and not PERFORMANCE.
The picture WILL be the same on 45nm for AMD - Sharikou will be yelling 40% higher speeds, like he did when 65nm was coming, (how them brisbanes clocking now, eh?). He will be in for a big thud, AGAIN, when AMD only gets power reduction and in all likelihood has a LOWER top speed bin than the previous node.
This is because AMD's transistors at the start of process are not up to snuff - they are essentially starting at the previous node's performance level (while Intel is at +30% of previous), and this is also why you can't simply compare the start of the Intel's and AMD ramps to look at how far apart the 2 ocmpanies are on technology. The reality is Intel remains ~2 years ahead. If AMD tried to match the Intel performance at the start of the ramps, 65mn would not even be out yet, and 45nm would be in the 2009/2010 range when AMD gets around to INTEGRATING high K / metal gate.
Yeah IBM announced they already have high K and metal gate... blah..blah..blah.. Do a google search fo SiLK which IBM touted many years ago, only for it to FAIL abysmally when they tried to actually integrate it. I think AMD realizes this which is why they are focused on comparing the timing of 45nm as opposed to PERFORMANCE as they will be able to pull the wool over the press's eyes (and AMD fanboys), while trying to figure out how to integrate a 45nm process.
BTW - Intel 45nm launch expected sometime late Q3/Q4. Latest AMD claim - launch H2'08. How is this "6 months at most" again as Scientia has claimed? And the performance when both companies launch the process will be comparable? (Answer: No... see 65nm ...)
The boy is clueless...
I love my MacBook Pro and can't wait to get an updated Santa Rosa based version. Yep, Intel made a smart move by convincing Apple to switch over to Intel Architecture.
Now let's hope both companies yield the dividends from their collaboration :)
A Letter to Hector Ruiz
http://www.dailytech.com/A+Letter+to+Hector+Ruiz/article7829.htm
Good read. Someone please post this for Scientia and Sharimoustache to read.
Anonymous said...
Scientia showing his (lack of) expertise in the Si processing area (AGAIN):
"Also, I've already seen the particle defect rate for AMD's 45nm immersion process and it is doing well."
He's talking about the particle rate on immersion vs dry litho - of course the OVERALL process yield is just a bit more significant than just that! (He's looking at 4 out of several hundred process steps, while also ignoring that smaller defects which might not have been a problem on 65nm might actually be a problem on a smaller node side - so equivalent defects is not actually the whole story). Perhaps he thinks that is the only change from 65nm to 45. Perhaps he thinks you get transistor speed from just making Lg smaller... (Or perhaps he doesn't have a clue, has found a single data point which actually would not be predictive of yield and is trying to confuse the masses?)
The other funny part is that he equates simple particle density to yield, there are NUMEROUS sources of yield issues outside of particles and short of AMD sneezing on the wafer he is missing the boat...
"If AMD follows pattern they will shrink the process a second time maybe Q4 07."
Shrink the PROCESS? WTF?!?! Shrink it from what to what? AMD may optimize the DESIGN and chip layouts better for 65nm and shrink products but they don't SHRINK the process a 2nd time (unless he's confusing speeding up transistor performance with SHRINKING the process). What is AMD running a 75nm process now? Or are they at 65nm and shrinking it to 60 or 55nm? Shrinking should not be confused with CTI or re-optiomiZing a chip layout. (this is not "shrinking the process")
"We can tell that things were not exactly up to speed with Brisbane because the die shrink was not that great on 65nm."
So the amount of die size reduction is proportional to increased speed? I guess in simplified Dementia world that is the case - the speed that AMD didn't get on 65nm was not because of the amount of "SHRINK", it was because the initial 65nm transistors were essentially glorified 90nm ones with smaller gate size (and Vt's). This is what Scientia has failed to understand all along when he compares how far behind AMD is with Intel on process technology. The 65nm process at ramp, didn't have many of the technology improvements, AMD was essentially (to dumb it down) printing 90nm transistors with 65nm features (In reality this is not quite true as they also retargetted Vt which is what gave the power improvements). However a lot of the changes to improve transistor
(strain, not sure about salicide) were yet to be implemented - this is far different from Intel which at technology node ramp has more or less gotten the final transistor performance (while they will tweak over the course of the node, they generally target a >30% improvement over the previous generation). This is why Intel is much farther ahead than AMD claims or it appears to the lay person. For AMD to catch up on things other than simple FEATURE printing they need more time into the ramp.
While AMD EVENTUALLY does the same they do not get there until much later in the node lifetime. So when he says "look AMD's only a year behind as they had 65nm products 1 year after Intel" or it will be 6 months on 45nm (through some complete lack of basic calendar skills), he is only compering SCHEDULE and not PERFORMANCE.
The picture WILL be the same on 45nm for AMD - Sharikou will be yelling 40% higher speeds, like he did when 65nm was coming, (how them brisbanes clocking now, eh?). He will be in for a big thud, AGAIN, when AMD only gets power reduction and in all likelihood has a LOWER top speed bin than the previous node.
This is because AMD's transistors at the start of process are not up to snuff - they are essentially starting at the previous node's performance level (while Intel is at +30% of previous), and this is also why you can't simply compare the start of the Intel's and AMD ramps to look at how far apart the 2 ocmpanies are on technology. The reality is Intel remains ~2 years ahead. If AMD tried to match the Intel performance at the start of the ramps, 65mn would not even be out yet, and 45nm would be in the 2009/2010 range when AMD gets around to INTEGRATING high K / metal gate.
Yeah IBM announced they already have high K and metal gate... blah..blah..blah.. Do a google search fo SiLK which IBM touted many years ago, only for it to FAIL abysmally when they tried to actually integrate it. I think AMD realizes this which is why they are focused on comparing the timing of 45nm as opposed to PERFORMANCE as they will be able to pull the wool over the press's eyes (and AMD fanboys), while trying to figure out how to integrate a 45nm process.
BTW - Intel 45nm launch expected sometime late Q3/Q4. Latest AMD claim - launch H2'08. How is this "6 months at most" again as Scientia has claimed? And the performance when both companies launch the process will be comparable? (Answer: No... see 65nm ...)
The boy is clueless...
26 June 2007 01:58
Quoted for truthiness.
I am alarmed at this statement. I really don't know how he gets away saying this things. Windows 3.0 had errors than this.
Scientia said: "AMD's 65nm process is yielding fine. K10 uses a slightly tweaked transistor, however, AMD has never dropped yield when updating a transistor so why would you think they've started now?"
I don't want to start an essay why this statement is obscenely incorrect.
Scientia showing his (lack of) expertise in the Si processing area (AGAIN):
good point AnonGuy. i don't understand why he continues to comment on semiconductor manufacturing with statements that shows his lack of understanding on the subject matter.
AMD's 65nm process is yielding fine.
Which is why Brisbane is clocked lower at stock, overclocks worse than F3 (90nm), requires more voltage at the same clock, has worse cache latency, not available in any reasonable quantities (where are the 45W chips).
Very few people are aware of this but Scientia has a red phone direct line which connects him directly with AMD headquarters and the Fudcave. His latest communique was to inform me that he has been able to completely confirm that K10 will be released by 5 pm tomorrow, and that he has independent, fully unbiased and completely credible benchmarks that show 3.15 PFLOPs which will handily beat IBM's Blue Gene even when the AMD chip underclocked by 10%, and all this while only drawing 9 W power and operating at 1.5 degrees C over ambient temperature even without a heatsink. Unfortunately I was at the drive in enjoying the bodacious anatomy of a hot blonde in the backseat of the Fudmobile and he only got my voicemail.
Scientia: "However, you need to consider that the ratio of die size to wafer size is actually smaller than what AMD has done in the past with K8 on FAB 30. Since these didn't cause any large drop in yield I don't see why K10 would."
Ahh, yield is proportional to ratio of die size to wafer size! BRILLIANT!
My thoughts? When your are looking at yields, you need to consider Scientia has no background in this area whatsoever. And the ratio of Scientia's yield knowledge to one's ability to learn about yield is constant (and zero).
So that 130nm process I'm running on 150mm wafers should be the roughly the same yield as say a 65nm process with a die 4X bigger?
Wafer size/die size?!? He just keeps getting better and better!
SCIENTIA" "There won't be any official word from AMD on K10 yields until the meeting in July."
Just remember everyone though, the meeting was delayed to better tell the analysts about DTX and the F30 conversion, it has nothing to do with K10 delays or lacj of detail available in June - if you have any disagreements with me on this, just reference Scientia's early blog on this.
Here's a guess on AMD's potential statements on K10:
"Yield is progressing on schedule"
"Yield is better than expected"
"We have the fastest yield learning ramp we have ever had with K10"
Notice how all of these carefully avoid saying good or bad, but will likely be misinterpreted by the mainstream press as meaning "good".
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