This a commentary reaction to Scientia's latest blog:
How we Got Here...
http://scientiasblog.blogspot.com/2007/05/how-we-got-here-x86-industry-in.html
"Since the separate Penium M line has now been abandoned in favor of the C2D Merom, we would seem to need one less design team. However, it is hard to believe that Intel which has always had three design teams is now down to just two: the Itanium and the C2D line. "
The history lesson is fine. The mistake is trying to tie-in R&D teams to released products.
The whole idea of trying to determine intel's design teams and design life cycle based on product releases is overly simplistic and completely wrong. Again, this is a common mistake of an outside observer.
There are multiple levels and teams of R&D affecting a product during its discovery, design and manufacturing phase. To say for example that Intel has "3 microprocessor design teams" is inaccurate. One can accurately say that intel has 3 microprocessor design integrators - which will be comprised of several design teams working on different architectural enhancements.
uArch enhancements done by pockets of R&D teams aren't product specific. uArch/ucode discovery which occurs 5-7 years before the technology is applied isn't product specific. For example, there are teams working on improving the ALU or the Scheduler and there are teams working on improving the integration of both. . There are different design teams working of different technology paths - and again, it isn't product specific. The same is true in process R&D. There are several R&D teams finding out solutions to problems we'll encounter 15 years from now. Even then discoveries are handed over to another team for development and then another team for deployment if feasible.
What is visible to an outsider like Scientia is the R&D team that responds to market conditions and tries to release a product based on demand and competition. This is just a tiny fraction of Intel's (and I'm sure AMD too) overall R&D headcount. This development/deployment team is defined based on what features/enhancement the CPU will have and is in fact very late in the R&D phase.
As for Intel's tick-tock strategy, what it means is that the number of product teams - design integrators are doubled. Instead of waiting and lumping all R&D discovered improvement in 4 year cycles, the idea is to leverage on R&D quicker and implement discoveries in an overlapping manner. 2 product teams in a 4 year cycle will result in a product family released every 2 years. So every year intel will either release a new product family or will move to a new process node.
5.13.2007
An Erroneous Outsider's View of the uArchitechture Design Process
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12 comments:
What an idiot.
roborat
"2 product teams in a 4 year cycle will result in a product family released every 2 years."
I had to laugh at this after you spent all that verbage splitting hairs.
you seemed to have missed the whole point. your oversimplistic and highly inaccurate guesswork of intel design team based on product release is what is laughable.
It's verbiage moron. You're one to talk. Roborat keeps it simple and gets it right. You don't.
"I had to laugh at this after you spent all that verbage splitting hairs.'
I had to laugh at seeing Scientia communicate in a single sentence - normally this type of response would require at least 5-6 paragraphs...
On a side not I love how he "figures out" (I think he says "bet") when design teams started based on his PERCEPTION of how long it should take an architecture to be designed and the subtracting it from the release date.
While 4 years is a reasonable enough benchmark to base assumptions on, to use that to determine when a design started is somwhat backward reasoning.
I can see the response now "well if this is not the case how is Intel going to release an architecture every 2 years?" (assuming 2 teams)
Answer - things are different now as Intel is targeting architectures based on an offset from manufacturing as opposed to market conditions / readiness. I am a bit concerned with this approach as it will likely lead to Intel being forced to drop a feature here or there as opposed to pushing out the schedule to get it done (the argument will be it can get caught up on the next 2 year cycle)
"This ability to isolate problem areas saves a great deal of iterative design work." (from S blog)
This is the theory - it has yet to be DEMONSTRATED. Isn't this same theory used in SW?
Or as a wise man once said:
"In theory, practice and theory are the same, in practice they are not."
Scientia works in theory space.... it's a lot easier just tossing out idle speculation without needing any data to support things. Yet when someone challenges his theories, you must prove them wrong - whereas in the normal scientific community it is generally accepted that onus in on proving the theory to be right...
Answer - things are different now as Intel is targeting architectures based on an offset from manufacturing as opposed to market conditions / readiness.
hasn't intel been releasing new product families offset from node transitions? I just think intel's tick-tock move is keeping in culture to be paranoid. Leverage on the massive R&D and implement quickly uArch discoveries.
"hasn't intel been releasing new product families offset from node transitions?"
They've been offsetting from node transitions, but not EVERY node transition. The u-arch was targeted for offset from a node tech, but generally speaking it was done when it was done (so long as it wasn't during a node ramp). With new strategy I think Intel will be more willing to put a time limit on the changes as if they miss the train with some change they can catch the next one in 2 years (as opposed to 4 or more years)
Holy crap, Scientia needs to be working for a politician as he is spinning expectations for AMD so low so that when AMD excceds this he can prop them up and spinning negative data like a top. A few examples:
"The latest news on K10 is not pessimstic. K10 was only supposed to launch at 2.3Ghz and the engineering samples are already running 2.4Ghz. Still, it don't mean a thing until AMD actually ships it."
Uh the planned launch speed for top product is 2.6Ghz. Scientia is downgrading this so that if AMD can actually meet their roadmap, he will say they are exceeding it...much like the 65nm timelines, Fx timeline and performance and 65nm process improvements back in Jan...
"In terms of market share it isn't clear that AMD has lost anything yet. Markets tend to be elastic for up to two quarters"
I think in Q4 , he was saying this as well...ah denial, what a wonderful thing...remember when Via's lost share was the reason for Intel's share increase (I think this was Q3)...
"AMD should be very competitive on the desktop in Q4 and should make a pretty healthy profit. Why would any of this be reason for concern?"
AMD is moving from a positon where they were TECHNICALLY SUPERIOR (K8 vs P4) for several years and managed to eke out some profit....now apparently "competitive" is a good position at the same time where they have taken on significant debt which will consume (I thnk) ~7% of AMD's revenue right off the bat.
Competitive = at the whim of Intel's pricing decisions. Superior means they can set the price somewhat independently (or at least higher) than Intel. Given the cost of production (and yield) differences between 65nm NATIVE and 65nm MCM quad core, simply being competitive in performance will put AMD in a very uncomfortable pricing position. Scientia also seems to be ignoring the fact that with lauch of DT in Q4, how much do you really think K10 will impact DT revenue?
"Intel should release some 45nm server chips but there is no indication that these will clock any higher than 3.0Ghz and this will not be fast enough to keep up with Barcelona's if they can clock to 2.97Ghz"
So we understand it is unreasonable to expect any clock increases as Intel switches from 65 to 45nm, while it is reasonable for AMD to have 3 Ghz chips when they are currently demonstrating 2.4Ghz chips and their own roadmap calls for 2.6Ghz? I do like the comparison - let's assume best case is Intel's CURRENT performance, and in AMD's case we'll assume some rumor of INQ or Fudzilla. I mean come on, talk about talking out of both sides of your mouth - don;t give Intel credit for anything higher becasue they haven't demo'd it or put it in a roadmap...yet on the other hand well put an AMD speed that has neither been demo'd nor put on ANY AMD ROADMAP!
"If this is the volume launch of K10 then this would match previous timelines." (referring to late Jul/early Aug)
Welcome to Scientia World where apparently volume means <~20% of SERVER production (which would be <7% of all production). Unless of course you are talking about Intel - then this would be a paper launch of course. I mean let's be clear Intel going from 0% to >50% of server chips on C2d in 6 months across multiple factories is a slow ramp... if AMD is able to pull this off in a single factory then I assume it wil be due to the magic of APM3.0 and AMD's superior process and manufacturing capabilities...
Welcome to Scientia World where apparently volume means <~20% of SERVER production (which would be <7% of all production).
i've said in the past that AMD cannot ramp Barcelon significantly using 65nm. Hard to conceive for anyone who hasn't worked in a fab but limited capacity are real issues a Fab owner faces.
Ruiz confirmed this by saying although Barcelona releases in 2007, it has no financial impact but only design wins. AMD will have to give up a significant chunk of marketshare if it wants to ramp Barcelona.
But guess what? Now that AMD has tons of inventory and smaller market share, maybe it can make a decent ramp after all. So watch out for that.
"But guess what? Now that AMD has tons of inventory and smaller market share, maybe it can make a decent ramp after all. So watch out for that."
Actually they can't do this - they will need to pump out some K10 dual cores to get some volume (and not to mention better yields!). They also don't have "tons of inventory" (as Sharikou also theorizes on his blog).
For about the fifteenth time - the inventory reported in the quarterly reports is a combo of finished goods, WIP (work in progress in the factory) and raw materials. I haven't run the #'s but I would suspect the biggest chunk of the increased Q1 inventory is the increased WIP due to F36 ramp increasing as well as increased raw materials (to support 2 fabs and increased wafer starts). In any event ~1/3 of the inventory is actually finished product...I'm basing this approximation on Intel's inventory reports which breaks out the inventory.
I'm really surprised to see desktop being the focus so shortly after server introduction - this is lowest margin of the CPU business and is also the slowest growing segment.
I think AMD is mistakenly assuming their growth in mobile (which has been one of AMD's highlights over the last year) will continue until they can get their new mobile core out (was this in 2008?) Yeah they are getting crunched on desktop right now and they may be trying to help get back the enthusiast crowd which they basically just told to F--- Off with the Dell deal and the last 2 quarters of screwing the channel which had been so loyal to them. AMD has to realize they need to cede market somewhere - why fight for desktop when that is slowest growing/lowest margin area?
Too much of a Napolean complex and fighting battles everywhere instead of focusing on a few key areas. (In my opinion)
I need some more sucking and fucking roborat.
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