7.02.2007

Another AMD Partner Warns - Soitec

AMD's major SOI wafer supplier issued a warning today:
Bernin, France, 2nd July 2007 – Soitec, leader in SOI (Silicon on Insulator) wafer material today announced that as expected the supply chain continued to absorb excess inventories held by its main customers throughout the first quarter… New products launched by main customers come on stream in the second half of the year but given the current uncertainty with regard to the timing of the ramp up in volume of these products, the Group cannot exclude that full year sales may be below the prior year.

Mark Osbourne insists that this is due to AMD.
"The key is volume ramp. AMD is the only Soitec customer that has major new products coming on-stream in that time. These products can equate to real volume ramp and could, in turn, impact the company's revenues by such a degree.So, in conclusion, the Barcelona volume ramp is delayed. Of more concern, though, is Soitec's unclear view as to when such a ramp will actually happen. That's the big new problem for both AMD and Soitec."

This isn't hard to believe. Nobody ramps a process when it is yielding less than 20%, let alone a very expensive die. It gets scary to think that AMD's partners don't have an idea when Barcelona will ramp. Put it this way, it takes months for SOITEC to prepare for Barcelona's volume ramp and if SOITEC hasn't received any orders and has no visibility for 2007, don't hold your breath for any miracles this year.

ATI, Chartered, Sun, Dell, Cray, and now SOITEC. From business units to customers and now suppliers. The downward spiral to bancruptcy begins with the collapse of the business ecosystem. This isn't very encouraging news by any measure and probably has greater implications to the SOI wafer industry. All of a sudden the SOI business becomes less attractive and may impact further cost improvements down the road to make it competetive against bulk.

4 comments:

Dr. Yield, PhD, MBA said...

Yes, but...

All of AMD's 65nm production requires 300mm SOI, Barcelona or not.

Fab loading on a built out fab should be fairly constant, so if anything, I would take this as an indication that the 300mm conversion/ramp is going slower than planned, and not anything particular to Barcelona, yield or otherwise.

Roborat, Ph. D. said...

dr yield said: "I would take this as an indication that the 300mm conversion/ramp is going slower than planned, and not anything particular to Barcelona, yield or otherwise."

True. But why would SOITEC mention "new products".

Anonymous said...

Dr yield is right on this one - unless one of a few things is occurring:

1) AMD is underloading their factories (as they use SOI for both K8 and K10)
2) AMD is ramping down 200mm (F30) quicker than expected - while these wafers are cheaper than 300mm they use more of them than 300mm.
3) AMD is using a more expensive rev of SOI on K10 over K8 - perhaps SSOI, or SOI with tighter specs than is used on K8, so a slowdown of the K10 ramp would shift SOI's mix toward cheaper SOI.

Otherwise it may just be SOITEC passing the blame, or it could be OTHER customers are slowing down transition to SOI (though this would have to be a major shift with multiple customers, as noone other than AMD is buying SOI in large quantities).

FYI - SOI will never be cost competitive with bulk. The gap may get smaller, but there will ALWAYS be a gap. The reason is you need a bulk wafer to make the SOI wafer, so unless the extra processing (whether it is the layer transfer process or the O implant process) goes to $0 (which it won't) it will always be more expensive. In fact as 300mm bulk wafers go down in cost that will put more pressure on the SOI cost competitiveness as the extra processing becomes a larger percentage of the overall cost.

The only real question on whether SOI becomes competitive to bulk is whether you can eliminate process steps on an SOI process. At this point, especially on a PD SOI process, this is not the case. However, all of the wannabe "process experts" like Scientia and the AMDroids don't seem to understand this.

Anonymous said...

OK, Scientia is really losing it now with his last blog (grasping at straws anyone?)

"It is likely that AMD does have at least some 2.2Ghz chips. We know that AMD is not saving these for Cray since Cray is waiting on Budapest however Sun might be waiting on faster Barcelona chips for Ranger which requires about 16,000. Or AMD may simply be stockpiling faster chips for Q4 release."

Funny didn't he previously indicate they had 2.4GHz chips? If they had 2.4GHz chips back then how is it now only "likely" that they have 2.2GHz versions?

The theory here is AMD is CHOOSING to stockpile chips while launching slower processors? 16,000 chips in NOTHING...at 160 chips/wafer this is 100 wafers! From a fab capable of starting 20,000 wafers/month, that would represent 0.5% of it's capacity! Of course if yields or binsplits are crap (which of course could never be the case for his beloved AMD), that is a different story...

"It sounds like the process has been tweaked a bit too much in favor of low power and that is why there aren't enough higher clocking parts."

Errr...no....if it were a PROCESS issue, new steppings wouldn't be fixing the speed issues, AMD would simply be needing new process revisions. In reality they need BOTH! This is where CTI, which sounds great on paper, now exposes its largest shortcoming.

Instead of rev'ing a design while having a stable process, or rev'ing a process with a stable design (which is Intel's approach with the tick-tock strategy), AMD is rev'ing both process and design, and has to deal with any interactions which could lead to more iterations... A design fix which works on process rev A, may suddenly have a different consequence on process rev B. This is especially true on process steps which are very sensitive to pattern - strain technologies come to mind as a good example and this is a key area which changes with AMD's CTI steps!

"So, most likely AMD's plan was to give this news quietly after Computex to allow a few weeks for it to settle and expectations to tumble accordingly. Then they could start the July 2007 Analyst Day on a more upbeat note"

Funny I thought the delay to analysts day was PURELY to hype up DTX and show off their F30 decommissioning... as Scientia had previosuly hypothesized! More upbeat? Let's see how the AMD PR machine works:

Step A: HYPE K10 before you really have working product by releasing simulations and claim a 40% advantage over your competitors best product. Choose a competitor product in the mid-year range by assuming everything on your end comes together perfectly. (otherwise you might have to compare your product to it's real competitor, Penryn, and you know there's no way of getting away with the 40% claims)

Step B: "Demo", and I use this term VERY loosely, an underperforming chip 3 months prior to launch at clockspeeds LOWER than the lowest expected launch speed. This will help crash the high expectations that were created, and thus hopefully people will forget about the original claims and use this poor performance as the new baseline expectation.

Step C: Announce product release at the lowest range and claim this as "what the customers want" and a focus on "energy efficiency"'. At the same time promise higher speed chips (but imply that you are just waiting on releasing these as customers are asking for low power chips). You have also now started to beat the low expectations you set at Computex...

Step D (projected): Release the low end parts in Sept, claim victory via power efficiency and drop in replacement capability. Maybe even throw in a new benchmark like upgrade cost per upgrade benefit per watt....Conveniently ignore the 40% claim and if anyone asks say you are customer-centric and you will deliver that 40% part when the customers demand it.

Step E (projected): Finally release mid range parts, say ~2.4GHz range, maybe even throw in a handful of cherrypicked 2.6GHz's which you can't make in volume. Claim a smashing success and flawless execution to the revised plan (while conveniently ignoring the ORIGINAL plan). Note to the press that the only reason you didn't achieve the 40% better was because your competitor now has faster chips and when you made that claim you weren't expecting this, thus the 40% claim can't really be invalidated...