12.20.2006

Clueless idiot posted this AMD die output estimate

Sharikou wrote an outrageous claim showing how little he knows about the semicon industry:

The 65nm Brisbane die size is 126mm^2, using a geometry of 11.5 x 11.5 for the wafer program, we find a 300mm wafer can produce 492 dies.At 18000 wspm at FAB36, quarterly die output is 18000*492*3 = 26.6 million.At FAB30 (90nm), the die size is 183mm^2, with a geometry of 14 x 14, a 200mm wafer produces 137 dies. At 30000wspm, quarterly die output is 12.3 million.Total AMD dual core die output 39 million per quarter.Throwing in Chartred FAB 7 at a small number of 2 million, we get 41 million dies/quarter.With a yield of 90% (that's right, pause for laughter here), we get 37 million dual core CPUs per quarter, leaving a 20 million market for Intel.Expect AMD to improve its 65nm transistor soon, and expect major clockspeed bump sometime next year.

I countered with this estimate:
Assuming your total Fab output is accurate for the first time:
41 million is the theoretical capacity - Fab true output (best case estimate) 95% (typical 90-95%) = 38950000
Subtract best case R&D, new product introduction, sample lots at 5% (usually 5-10%) = 37002500
Subtract Fab mechanical yield loss (defectivity, process missteps) best case 10% (usually 10-20%) = 33302250
Subtract Assembly mechanical yield loss (die to package) best case 10% (usually 10-15%) = 29972025
Subtract Electrical yield loss (bad die, low bin, infant mortality) best case 15% (usually 15 – 40% depending of maturity) = 25476221

25.4 million die per quarter is about 62% yield.

And this is just best case, not even Intel can achieve this consistently at mid process maturity. AMD is lucky it can even get 50% wafer-to-unit yield on a process and equipment-set they did not develop themselves. That's right, IBM owns the silicon design rules while it is Intel who gets first development on capital equipment makers such Applied Materials for equipment enabling. Most capital equipment are developed under Intel process influence since they are always ahead. AMD using similar tool sets are only refined tools to meet their process. Because of this AMD can never have better yields than Intel unless they lead in process technology.

Now, assuming at 50% yield 41 million is only down to 20.5 million. And this isn’t even taking into account AMD's Fab transition in the next few quarters. 20.5M/Qtr is more in-line with reality.

2 comments:

Sharikou, Phd said...

Fine! I must admit, I didn't know what I was talking about.

Anonymous said...

First - love the blog title.

Second - our starting point of 41mil was off on thoeretical die because Sharikou was printing die to 0mm edge exclusion and assuming dicing consumed 0 Si between the die.

Putting in normal assumptions this is yet another 10% error in theoretical max...