2.12.2008

Intel and the European DisUnion

I assume everyone is aware that Intel's Munich office along with major computer retailers have been raided.

EU regulators raid Intel offices

BRUSSELS (AFP) — EU antitrust regulators stepped up a probe into microchip giant Intel on Monday by raiding the US company's German offices and computer retailers on suspicions they might have stifled competition.
The European Commission "has reason to believe that the companies concerned may have violated (EU) rules on restrictive business practices and/or abuse of a dominant market position," a statement said. It did not disclose the number or names of companies raided, or divulge where they took place, saying only that "commission officials were accompanied by their counterparts from the relevant national competition authorities."


On the surface there seems to be nothing new here as the EU's obvious distaste for dominant American companies is pretty much well established. It is the behind the scene involvement of the German government that raises a few eyebrows. There is an obvious element of politics involved here and AMD seems to know where and when to pull the strings. One thing anyone needs to know about the European Union is the dis-unity. Behind the curtain, everyone is either fighting for it's own interest, or politicians trying to seek re-election.

Maybe Intel is indeed guilty of violating the EU's competition law and deserve what they got. But then again maybe someone is just trying to save face. Some politician isn't looking good at the moment after granting €262M last year to AMD after promising to run 2 Fabs. Seeing that the AMD bet is a mistake it isn't too hard to imagine why anyone want somebody to blame. In fact it happens more frequently than you think. You have another New York politician who has wasted millions in setting up the infrastructure for an AMD fab that isn't going to happen. Guess what happens next? (Intel gets a subphoena).

101 comments:

SPARKS said...

Zig Heil! Der EAU is at it again with Gestapo raids at dawn at Intel Head Quarters. Can you imaging the FBI raiding a European company here in this country? The international diplomatic fallout would reach scandalous proportions. I suppose AMD needs all the help they can get at this juncture.

So much for the 250 million dollar investment in AMD’s FAB, they’ll get their money back, one way or another.

Bastards.

http://www.theinquirer.net/gb/inquirer/news/2008
/02/12/
eurocrats-swoop-intel-dawn-raid



SPARKS

Chuckula said...

Here's the problem with Anti-trust:
Say Intel raises prices: HOW DARE INTEL USE ITS MONOPOLY TO HURT CONSUMERS.

OK, Say Intel lowers its prices: HOW DARE INTEL HARM ITS COMPETITORS WITH "UNFAIR" PRICES.

Say Intel comes out with new chips: THIS ISN'T FAIR, AMD CAN'T COMPETE, INTEL IS CORNERING THE MARKET.

Say Intel holds off on new chips: WAH!! INTEL IS STOPPING ALL PROGRESS!!!

You get the idea, there is nothing that Intel CAN do that will make anti-trust whiners happy. The Europeans are also way behind the curve since they are still stuck in the 1930's mindset that there is some duty to keep AMD on life support, even if this means harming customers by making worse chips more expensive. At least in the US they've partially figured out that anti-trust is NOT a tool whereby second-rate players can steal from the big dogs, but it should only be invoked when a trust is actually abused. to the harm of consumers.

For all of AMD's whining, they still come out and brag about how they sell out all the chips they can make (once they slash prices in ways that would have people screaming if Intel did the same thing) and have a big share of the retail market, have all these design wins, etc. etc. Even the other day one of AMD's marketing executives said it was good for AMD when... INTEL advertises because many people go out and buy a computer with an AMD chip in it because they don't really pay much attention. It sounds more like AMD survives BECAUSE Intel is big rather than Intel somehow ruining AMD's business.

On a completely unrelated note: I built the new e8400 system. The first mobo from Asus was faulty however, and I just got the RMA back today (It's the X38, DDR 2 Maximus Formula). Anyway.... the chip clocks up to 3.6Ghz with the only effort being a tweak to BIOS, and it's running Kubuntu at an insane speed. I know I mentioned watching HD video as a problem... well I can watch 2 1080p videos while doing 3D desktop scaling LIVE. About the only problem is that the Intel audio isn't being picked up by the drivers yet, that should hopefully be fixed in software soon. Yeah, I'm so hurt by Intel "forcing" me to buy better chips.

S said...

It is obvious that these are AMD's dirty tricks. Last couple of anti-Intel actions have happened in the locations where AMD has business interests. This is not a coincidence.

Tonus said...

It can also be a pretty big notch in an investigator's or government agency's belt if they can take down a large company that isn't playing by the rules. I don't think they're accusing Intel simply of using pricing pressure to hurt AMD, I assume that they are accusing Intel of bullying or coercing retailers in some manner. How office raids would gather evidence of this, I'm not so sure. I think the raids are more for PR impact, because people may think "why raid the offices, unless... THEY'RE GUILTY!!!"

Unless they find a smoking gun, I doubt much will come of it. When you have companies like MS and Intel, that are so large and entrenched, with no real competition that can just step in and take over, you can't really try to hurt them too much. What they are probably hoping for is some sort of agreement or small fine. Something that makes them seem like tough lawmakers who gave the big bad corporation a black eye, while not really having an effect on Intel one way or another.

Anonymous said...

The Germany stuff - conflict of interest + going after an American company in an environment which is sypathetic to this. The NY stuff I suspect is more politics than about the NY fab subsidies (though the subsidies is probably not a complete non-factor in this).

Every major politician/lawyer in NY is looking to move up. You have these guys investigating Intel, investigating the mortgage companies, going after Amazon etailers for sales tax collection, and I can go on and on... Basically you take out a shotgun - go after BIG BAD CORPORATE America and hope you hit something. That state is so damn liberal that if you manage to 'bag' a big business, you can become Mayor, Governor, or a senator with aspirations toward the presidency.

Cuomo, Spitzer, et al... are not about the good of the people, they are about moving up politically. Having previously lived in NY for 18 years it is sad how they pawn this off as for the good of the people, when it is simply pursuit of personal ambition...

Anonymous said...

AMD is down and out. Isn't it humorous that the two places still pursuing INTEL happen to be a place where AMD does all its manufacturing and another place AMD is promising to build a multi-billion factory.

Oh, and the two locations that are raiding are the ones that have or promise millions upon millions of help to AMD.

Get real, bias is everywhere.

Perhaps AMD should stop spending time and energy trying to sue others and blaming others for their failures.

Perhaps Hector and Dirk should focus on fixing Barcelona, getting next generation designs out on time, getting 45nm implemented, fixing 65nm yield and speed, and pulling in 32nm. Too bad they still are obessed with how someone else causes their own failures versus looking in the fucking mirror

Anonymous said...

"Perhaps AMD should stop spending time and energy trying to sue others and blaming others for their failures."

I tend to agree with the current set of problems. AMD and/or governments has the right to pursue this for potential past transgressions, but clearly the 'monopoly' is not the cause of the AMD's current problems. I think AMD's mgmt conveniently intermixes these hoping folks may not realize this distinction.

My question is this though... is the EU looking for recent stuff (within the last 2 years say) or older stuff? And what exactly is the SPECIFIC damage done to the EU? I can see AMD trying to make a claim (if anything is proved) but what about the EU? If rebates or whatever is deemed anticompetitive then I can see how this impacted AMD, but if the prices that consumers were paying were still low and competitive (like they are now), how exactly is the EU consumer injured? These are not European companies. Does the EU fine companies who sell clothes in the EU that are done by labor at ridiculously low salaries?

This, to me, in disingenuous. If the argument is that consumers got hurt then I eagerly wait to see if the EU distributes checks to all those who purchased a computer in that time period they allege (should they actually levy a fine). Somehow though, I don't think we will see that (call me a cynic).

If the issue is that AMD was injured, than AMD (NOT THE EU) should be the ones pursuing this as they are doing in the US.

Anonymous said...

However, as I know AMD / Hector's original claims is during 2003/2004 where the K8 structure as an obvious advantage over P4 / PD, but unable to grow immediately like Intel's core series due to "Intel's practice".

The case seems to drag on and not related to AMD current possition which is more because of ATI aquisition and K10 issues.

Anonymous said...

Apparently the sequel for 'There Will be Blood' is due out in Q2'08:

http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=CPFVA3ZSZLR5AQSNDLPCKH0CJUNN2JVN?articleID=206503146

"AMD sees 'glitch' in Puma platform, says analyst"

If true, and AMD insists this is not true, this could be an even uglier year - notebooks is where AMD has been able to make some headway and in my view this was the one real potential way AMD could make some movement in overall ASP (while server ASP's will likely get somewhat better with K10, the volumes are low enough where it will not majorly impact overall #'s)

Of course rumor has it Intel's monopoly power may be responsible for this 'glitch'; the EU is closely following the situation and may launch another investigation.

HECTOR RUIZ said...

http://www.nvidia.com/object/io_1202940080671.html

NVIDIA Reports Record Results for Fourth Quarter and Fiscal Year 2008

Company Achieves Record Quarterly Revenue and Record Annual Revenue; Annual Net Income Increases 78 Percent Year-Over-Year
For further information, contact:

Michael Hara Calisa Cole
Investor Relations Corporate Communications
NVIDIA Corporation NVIDIA Corporation
(408) 486-2511 (408) 486-6263
mhara@nvidia.com ccole@nvidia.com

FOR IMMEDIATE RELEASE

SANTA CLARA, CA—FEBRUARY 13, 2008— NVIDIA Corporation (Nasdaq: NVDA), the world leader in visual computing technologies, today reported financial results for the fourth quarter of fiscal 2008 and the fiscal year ended January 27, 2008.

For the fourth quarter of fiscal 2008, revenue increased to a record $1.20 billion, compared to $878.9 million for the fourth quarter of fiscal 2007, an increase of 37 percent. Net income computed in accordance with U.S. generally accepted accounting principles (GAAP) for the fourth quarter of fiscal 2008 was $257.0 million, or $0.42 per diluted share, compared to net income of $163.5 million, or $0.27 per diluted share, for the fourth quarter of fiscal 2007, a net income increase of 57 percent.

Non-GAAP net income for the fourth quarter of fiscal 2008, which excludes stock-based compensation charges, a charge for in-process research and development related to an acquisition closed during the quarter, and the associated tax impact, was $292.6 million, or $0.49 per diluted share.

Annual revenue for the fiscal year ended January 27, 2008 was a record $4.10 billion, compared to revenue of $3.07 billion for the fiscal year ended January 28, 2007, an increase of 34 percent. GAAP net income for the fiscal year ended January 27, 2008 was $797.6 million, or $1.31 per diluted share, compared to GAAP net income of $448.8 million, or $0.76 per diluted share, for the fiscal year ended January 28, 2007, a net income increase of 78 percent.

Non-GAAP net income for the fiscal year ended January 27, 2008, which excludes stock-based compensation charges, a charge for in-process research and development related to an acquisition closed during the year, and the associated tax impact, was $919.3 million, or $1.56 per diluted share.

"Fiscal 2008 was another outstanding and record year for us. Strong demand for GPUs in all market segments drove our growth. Relative to Q4 one year ago, our discrete GPU business grew 80%. Our growth reflects the ever-increasing use of rich graphics in applications from Google Earth to Apple iTunes to online virtual worlds," said Jen-Hsun Huang, president and CEO of NVIDIA.

Mr. Huang continued: "This is the era of visual computing. The richness of the graphics is increasingly central to our computing experience. And at the core of that experience is the GPU, the processor that defines the modern PC."

Fourth Quarter, Fiscal Year 2008, and Recent Highlights:

* Fourth Quarter revenue grew 37 percent year-over-year to a record $1.20 billion.
* Annual revenue increased 34 percent year-over-year to a record $4.10 billion.
* GAAP annual net income increased 78 percent year-over-year to a record $797.6 million.
* GAAP annual gross margin reached a Company high of 45.6 percent, a year-over-year increase of 320 basis points.
* We launched multiple industry-defining products and initiatives:
o GeForce® 8800 graphics processing family, including the highly-acclaimed 8800GT < li>GeForce 7000 mGPU – the first single-chip motherboard GPU for Intel systems
o Tesla ™ computing system – the high performance computing industry's first C-programmable GPU
o Hybrid SLI® technology – the first hybrid technology for PC platforms
o CUDA™ technology – the first C-compiler for the GPU
o PureVideo® HD technology – the first video decode and post processing technology for Blu-ray and HD DVD
* NVIDIA® held #1 segment share in desktop and notebook GPU (Mercury Research PC Graphics 2008 Market Strategy and Forecast Report).
* NVIDIA held #1 segment share in workstation solutions (Jon Peddie Research Q3'07 Workstations and Professional Graphics Report).
* NVIDIA was named Most Respected Public Company by members of the Fabless Semiconductor Association for the second consecutive year.
* NVIDIA was named Forbes Company of the Year.
* We acquired Mental Images, the industry's leading photorealistic rendering technology provider. Mental Image's Mental Ray is the most pervasive ray tracing renderer in industry.
* In February, we announced and completed the acquisition of AGEIA, the industry leader in gaming physics technology.

Conference Call and Web Cast Information
NVIDIA will conduct a conference call with analysts and investors to discuss its fourth quarter fiscal 2008 financial results and current financial prospects today at 2:00 P.M. Pacific Time (5:00 P.M. Eastern Time). To listen to the call, please dial 212-231-2901; no password is required. A live Web cast (listen-only mode) of the conference call will be held at the NVIDIA investor relations Web site www.nvidia.com/investor and at www.streetevents.com. The Web cast will be recorded and available for replay until the Company's conference call to discuss its financial results for its first quarter fiscal 2009.

Non-GAAP Measures
To supplement the Company's Condensed Consolidated Statements of Income presented in accordance with GAAP, we use non-GAAP measures of certain components of financial performance. These non-GAAP measures include non-GAAP gross profit, non-GAAP net income, and non-GAAP diluted net income per share. In order for our investors to be better able to compare our current results with those of previous periods, we have shown a reconciliation of GAAP to non-GAAP financial measures. These reconciliations adjust the related GAAP financial measures to exclude stock-based compensation, patent license fees for past usage, in-process research & development charges related to acquisitions, a non-recurring credit associated with the net cumulative impact of estimating forfeitures as a result of the adoption of SFAS 123R, and the associated tax impact, where applicable. We believe the presentation of our non-GAAP financial measures enhances the user's overall understanding of our historical financial performance. The presentation of our non-GAAP financial measures is not meant to be considered in isolation or as a substitute for our financial results prepared in accordance with GAAP, and our non-GAAP measures may be different from non-GAAP measures used by other companies.

About NVIDIA
NVIDIA is the world leader in visual computing technologies and the inventor of the GPU, a high-performance processor which generates breathtaking, interactive graphics on workstations, personal computers, game consoles, and mobile devices. NVIDIA serves the entertainment and consumer market with its GeForce products, the professional design and visualization market with its Quadro® products, and the high-performance computing market with its Tesla products. NVIDIA is headquartered in Santa Clara, Calif. and has offices throughout Asia, Europe, and the Americas. For more information, visit www.nvidia.com.

Certain statements in this release including, but not limited to, statements as to: the use and importance of graphics; visual computing; and the role of the GPU are forward-looking statements that are subject to risks and uncertainties that could cause results to be materially different than expectations. Important factors that could cause actual results to differ materially include: slower than anticipated adoption of new technologies or development of a market; the impact of competition and competitive products; technological advances; the development of more effective or efficient GPUs or CPUs; changes in consumer preferences or product uses; incompatibility of technologies; changes in industry standards; as well as other factors detailed from time to time in the reports NVIDIA files with the Securities and Exchange Commission including its Form 10-Q for the period ended October 28, 2007. Copies of reports filed with the SEC are posted on our website and are available from NVIDIA without charge. These forward-looking statements are not guarantees of future performance and speak only as of the date hereof, and, except as required by law, NVIDIA disclaims any obligation to update these forward-looking statements to reflect future events or circumstances.

###

Copyright® 2008 NVIDIA Corporation. All rights reserved. All company and/or product names may be trade names, trademarks and/or registered trademarks of the respective owners with which they are associated. Features, pricing, availability, and specifications are subject to change without notice.

Note to editors: If you are interested in viewing additional information on NVIDIA, please visit the NVIDIA Press Room at http://www.nvidia.com/page/press_room.html


Intel and Nvidia report record profits and record revenues while AMD reports RECORD LOSSES.

Anonymous said...

Dear Hector - how about just posting the link above and letting people view it that way? (Or do you get paid by the word?)

Anonymous said...

OR This could simply be a fishing expedition to create a climate of fear - Lets see how it pans out

SPARKS said...

Ah yes the EU. The group, whose history is replete with some perverted twisted sense of entitlements, has found a new venue to exercise self appointed authority.

Given the opportunity they have, and always will, be intoxicated by power and authority, and ultimately, as history has shown, will abuse it. The French, English, and Germans, especially, have now created a new Empire in which they can collectively assert global dominance in the world market. (We knew this would happen, didn’t we?) I need not go into the gory details of their collective contributions to world history over the last millennium. History speaks for itself, therefore, ‘Sun never sets on the EU Empire’.

Now they dictate policy over a market battle between two AMERICAN!!! companies. Absurd!

Zeig Heil!

Call me a bigoted, but I am not far removed from their past transgressions, as my fathers 57th Fighter Group chased the goddamned Nazis out of North Africa (Oil), thru Sicily, and ultimately kicked the shit out of them in Italy.

Too bad; yes, I’m an ugly American.

However let’s get a little more current, shall we? As AMD readies it newly relabeled DOG, Barcelona, with its B3 stepping in April, guess who is going to cut it prices on strategic quad cores at the same time?

You’ve got it boys and girls. AMD must lower its intro (read: re-intro) prices on the “new” B3 chips. Factoring in the delays, the cost of revisions, die size and yields, shitty process, lack of performance, and low margins (if any), I am going to stick my neck out and say that Barcelona will NEVER make ANY money for AMD, EVER.

Love him or hate him Ed at Overclockers has an interesting point of view, and I think he’s got this one right.

Further, I wonder what the EU will think about these price cuts, hmmm?

F@#& ‘em!


http://www.overclockers.com/tips01293/

SPARKS

Anonymous said...

ATI/NVIDIA to bankrupt soon:

http://www.s3graphics.com/en/products/chrome_400/

INTEL/AMD to bankrupt soon:
http://www.via.com.tw/en/products/processors/isaiah-arch/

You heard it first from me here at robo blog!

Anonymous said...

Wooo just amazing.

VIA has put more features on their new GPU than Nvidia.

VIA has put the same features existent in any advanced CPU from AMD and Intel.

I wonder how a less resourcefully company can beat Nvidia in Dx10.1 for example.

Now I see why Nvidia has bought Aegia, the company his hitting stagnancy...

VIA normally is 2 years behind or more, I wonder if this are the results of monopolies, when you have no competition you do nothing then the “dead” competition starts to keep up because the leader does nothing.

Anonymous said...

http://www.tomshardware.com/2008/02/16/_exclusive_dell_set_to_introduce_amd_tri_core_phenom/

Well it seams we will see 3.0Ghz Phenoms after all, but triple core.

Interesting, I wonder if AMD will also release Phenom dual core CPUs with two or three cores disabled, since they can make money with them instead of throwing them away. Assuming they have yields problems of course.

Interesting roadmap too.

SPARKS said...

If you think AMD is going to have an easy time of selling triple cripples, (and make money), think again. First there is this:


http://www.tomshardware.com/2008
/02/13/wolfdale_shrinks_transistors/



If you still have any doubts about that, then there is this:

http://www.fudzilla.com/index.php?option=
com_content&task=view&id=5698&Itemid=1


Incidentally, there is a lot of noise being generated DELL’s new 7XX Optiplex series of Pheromone, triple cripple, equipped machines. I’ll bet these things will be at the low end, of the low end, workstation crowd. Further, DELL had to get them for a song! Read: One mans junk is another mans…………!

SPARKS

Anonymous said...

"Well it seams we will see 3.0Ghz Phenoms after all, but triple core."

Did I miss the part showing clockspeeds? I didn't see any 3.0GHz in there - is that speculation or do you have a link?

"Interesting, I wonder if AMD will also release Phenom dual core CPUs with two or three cores disabled"

There are diminishing returns at a certain point - these things stil have to be fused (even if they broken), there are HT implications on how the cores are connected and just how would a dual or solo cripple core compete against a regular AMD K10 dual core (not to mention the Intel counterparts). Where would you price these things at? Below a 'regular' K10 dual core (such hat you eat into those sales) or at the same price? If the same price wouldn't you prefer the 'regular' dual core?

If their yields/process is really that bad that they need to sell nonfunctional dual and single cores, then they should just give up on monolithic quads altogether on the current generation and wait for 45 or 32nm and just make dual cores in the meantime.

I find it amusing that AMD has called the desktop quad core a niche segment (which, in fairness, it probably is at this point)... yet they have a crazy # of SKU's to satisfy this 'niche' market (and apparently because customers are demanding it?!) They will soon have a 1.8, 2.2, 2.3, 2.4, 2.6 (and potentially at some point a 2.8?), not to mention a bunch of tri-cores... all to feed what they themselves have claimed is a niche market. Rather interesting where the AMD spin leads you.

Anonymous said...

"....triple cripple, equipped machines. I’ll bet these things will be at the low end, of the low end, workstation crowd."

Low end workstation crowd? You're telling me people putting together workstations (and these are ostensibly people who have a use for multicore)... would take a tri-core that is slower both clock for clock and with the actual clockspeed than a $227 quad core come April?

Even if these cripple go for $120... why would you bother with something that likely is designed to use multicore and could use both the core count and the raw clockspeed. An extra $100 or less, when considering the cost of the ENTIRE workstation, seems like a good price for an extra core and a faster clock, no?

Tri-core, in my view, seems marketed at the less than intelligent dual core crowd who thinks an extra core is better even though the chip may be operating at 30% or more slower clocks than a comparably priced dual core. I'm sure they will sell to the "3 cores must be better than 2" crowd, but is there really a need for this? If you don't need a quad core (which many folks won't), then it is unlikely you'll need a tri-core either.

I wish AMD would just call a spade a spade... this is an attempt to recover some potentially lost yield on quad core wafers. I have no problems with this... just don't make up some marketing spin about this filling a market need.

SPARKS said...

“Low end workstation crowd? You're telling me people putting together workstations (and these are ostensibly people who have a use for multicore)... would take a tri-core that is slower both clock for clock and with the actual clockspeed than a $227 quad core come April?”

Easy, Rambo, don’t kill the messenger! It’s not my idea, its Dell’s. They are thinking about pawning these things off as Optiplex Workstations. Here’s the link.

http://www.engadget.com/tag/Phenom/


I realize, of course the whole shebang is absolutely ludicrous when faced with INTC’s myriad of (terrific) processor options; however, DELL has sold such nonsense in the past. So has AMD.

Caveat Emptor

Loves and kisses,

SPARKS

SPARKS said...

For your pleasure.

http://www.tomshardware.com/
2008/02/16
/_exclusive_dell_set_to_introduce_a
md_tri_core_phenom/

Enjoy!

SPARKS

SPARKS said...

Now, if I were to build a workstation, this would be MY weapon of choice. QX9650 would work very nicely for a top notch machine. A slight overclock, say 3.6 GHz w/ Zalman LED9500.

http://usa.asus.com/products.aspx?l
1=3&l2=82&l3=593&l4=0&model=1899
&modelmenu=1

Graphics, of course, would be application dependant.

Your pick:

http://www.cad2
.com/graphics_cards/index.htm

SPARKS

Anonymous said...

See video:

http://streaming.oracle.com/ebn/2007/6001335_300.rm

Intel BK by 1Q09.

SPARKS said...

Ha! The Empire Strike Back. Nvidia is going to take this one in the keester, and it's about time!



http://www.xbitlabs.com/news/video/display/20080222132030
_Nvidia_s_SLI_May_Disappear_or_SLI_
Policy_May_Be_Changed_If_Nvidia_Fails
_to_License_Intel_s_Next_Gen_Processor
_Bus.html

SPARKS

Anonymous said...

"The Empire Strike Back. Nvidia is going to take this one in the keester, and it's about time"

What's good for the goose....

Nvidia is whining about access to CSI... yet refuses to open up access to SLI... apparently it is Nvidia's right to be the sole supplier of chipsets to be able to access multiple Nvidia cards, but they expect they are entitled to full chipset access to Intel CPU's?

Sounds like a bit of an untenable situation for Nvidia... is it better to lock up access to multi-GPU chipset solutions on the Intel-side at the expense of no access to the next gen chipset biz? Seems like an easy decision to me.

With ATI starting to hit back in the mainstream discrete biz and Intel lurking in the future (2010)... Nvidia's high flying run could be slowing down just a tad...

SPARKS said...

“With ATI starting to hit back in the mainstream discrete biz and Intel lurking in the future (2010)... Nvidia's high flying run could be slowing down just a tad...”

I can recall the world before Core 2 architecture, quite well. AMD’s bravado and arrogance was only superseded by its own shortsighted, and now historic, long term strategic business failure.

Conversely, ATI (when it was a separate entity) worked, and played well with others. Ironically, as it turns out, it is now failing AMD’s strongest asset as ATI’s business approach, set it motion years ago, still retains much of that foundation when it was a separate entity. AMD is wise to capitalize on these assets. Frankly, they’re left with no other choice.

More to the point, arrogant bastard, Jen Sing Hung, is afflicted with the same short term great run of the 8800 series as AMD was with Athlon before C2D. This is stupid and short sighted. What a goddamned fool! Now was the time to throw INTC an olive branch, emphasize it’s (CORE!) business, graphics, open up SLI, and virtually become an INTC partner while AMD/ATI was and is on the balls of it ass!

No. This arrogant megalomaniac thinks HE is going take on the entire computing world while others cheerfully license their technologies to suit his singularly entitled goals.

If that MORON thinks he is going cut further into INTC chipset market, he’d better wake up and smell the TEA. Further, can you imagine if INTC licenses CSI to AMD/ATI and not NVDA?????

Holy, Christ, the future of the Computing world are still very much up in the air with the ATI/AMD merger. That said, love it or hate it, INTC dictates market dynamics. I think this is what is eating this bitch, as he seeks to be a computing GOD.

What NVDA doesn’t realize is that they are part of a very large picture, and they NEED each other. Success, obviously, has its pitfalls, and is fleeting. INTC learned this the hard way a few years back, so did AMD.

It’s now NVDA’s turn.

You don’t tug on Superman’s cape.
You don’t spit in the wind.
You don’t pull the mask off the Lone Ranger.
And, you mess around with INTEL.

SPARKS

pointer said...

Just being curious, NVIDIA by limiting the SLI to its own chipset, does that bring +ve business benifit or -ve buisness benefit in short term and long term?

Opennig up, they can sell more GFX card in Intel plartform, Limiting it, they can sell more NVIDIA chipsets due to the differentiation. I wonder if selling more chipsets can bring in more economical return or are there some implicit benefits that I do not know off (may be such as controlling the platform trend ...)

Anonymous said...

'Further, can you imagine if INTC licenses CSI to AMD/ATI and not NVDA????? '

Well I think it's a given that Intel will license to AMD/ATI... they have no interest in the Intel chipset biz and while AMD is stupid, to throw away ~75% (or greater) of the market for discrete cards would be insane.

I could see a crazy deal where Intel licenses it to Nvidia only for discrete graphics cards and doesn't allow it on chipsets unless Nvidia opens up SLI. Heck, even ATI allows crossfire on Nvidia chipsets - it's just that Nvidia doesn't want to do it.

Unless Nvidia is planning on buying/merging with AMD, they best start cozying up to Intel or else they will be relegated to fighting for scraps on AMD based CPU's, which last I checked favor the 'value' (read cheap) market and represent represent only ~25% of the overall market.

InTheKnow said...

Well, Scientia's latest blog was almost provocative enough to get me to post there. Almost, but not quite.

The first thing that I find interesting is that the "analysis" starts in 2003 and ends in 2006. It's rather curious that 2007 seems to have passed without being accounted for. Now on to specific points.

Let's start with the argument that AMD has been generations behind Intel in terms of process technology.

He then goes on to compare clock speeds. Last I checked, process tech wasn't clock speed. It was the things you were doing with the Si at the manufacturing level. So let's look at this statement from this perspective and see what we get.

From an SST article in Nov '07 we get this tidbit.

...Intel launched the 90nm Prescott chip in January 2004. The chip sported a number of significant process innovations—the first application of strain to transistors in a commercial product (both nMOS and pMOS), the introduction of low-k dielectrics, and the first use of nickel silicide.

That gives Intel Strained Si, low-K dielectrics and nickel silicide in 2004.

AMD claimed:
We promised 90 nanometer revenue shipments in the third quarter, and today we're delivering on that promise," said Dirk Meyer, executive vice president of the Computation Products Group at AMD. in mid Aug '04. 9 months behind Intel. AMD introduced Si strain on 90nm as did Intel. This puts AMD 9 months behind Intel on strain.

I've been unable to find anything indicating that AMD is using Nickel Silicide. An interesting aside is that I did see a lot of research from AMD touting Nickel Silicide as a replacement for SiO2 gates, but that seems to have dropped off the roadmap.

AMD does appear to have the edge with introduction of low-k dielectrics on the 130 nm node.

At 45nm of course the big news is high-k/metal gate. Intel will have that one for at least a year, maybe two before AMD goes that route.

AMD also introduced SOI at 130nm. This technology does confer some benefits. The debate is whether the benefits are worth the costs. But we'll give AMD the benefit of the doubt on this one.

So I see Intel with a lead of at least 9 months or more on 3 process technologies and AMD with 2 (both at 130nm). AMD was clearly introducing new tech faster than Intel at 130nm and has not been since. So since 130nm this gives a clear edge to Intel as claimed by the "nutty" press.

Next we have this:
The second argument is that AMD has been doing much worse with 65nm than it has before with process technology and is way behind where it should be. This is not exactly true when compared to AMD's previous track record with 130nm SOI.

I have one simple question regarding this statement. What happened to 90nm? Did this get left out because it didn't support the conclusion? From what I remember AMD's transition to 130nm was considered to be disastrous. One wonders why a train wreck of a process change was chosen as the reference point.

And finally, we come to this:
The third argument is that AMD's 65nm process is broken.

He argues that speeds can't be used as the discriminator here, and I agree. However, something does seem to be wrong as both K8 and K10 have both performed poorly at this node.

My suspicion is that AMD has combined the wrong architecture with this process node similar to Intel's 90nm/Prescott combination. That same process node produced a good product in the 90nm/Pentium M combo. So I would conclude that AMD has hit the thermal wall on 65nm just as Intel did at 90nm and needs a micro-architecture that will allow them to compensate for that.

One point I will agree with in principle is the following:
However, the reality is quite a bit different from such a superficial view. In between the period of 2003 and 2006 both companies shifted to dual core on P4 and K8 which slowed clock increases. We really can't compare one to one a dual core Tulsa at 3.8 Ghz to a single core Northwood Xeon at 3.46 Ghz. We clearly saw that even though AMD's 90nm process was mature by 2005 the initial clock speeds for X2 were 400 Mhz slower than the single core speeds. Adding in the core doubling factor we can see that the actual clock increases were greater than the apparent increases. Similarly today we see speeds being held back because of a shift from dual core to quad core.

Clock speeds alone aren't an indicator of performance. Multi-core and micro-architecture also have impacts. The total package is best evaluated through extensive benchmarking.

It does seem odd that all of the precede analysis was based on a that "superficial view", however.

SPARKS said...

“Just being curious, NVIDIA by limiting the SLI to its own chipset,”


Great question. We, as enthusiast and/or buyers, have grown accustomed to NVDA unprecedented deliberate limitation, which in fact, has been contrary to what brought the entire industry together over two decades ago. The ISA or Industry Standard Architecture was the coalescent force that brought the industry to where it is today.

Some may say it’s not the same thing. Really? Imagine for a moment if only Intel made it impossible for other companies to produce motherboards that would support 2X, quad core processors, giving INTC a clear and outright advantage in the market. All hell would break loose, trust me. Intel could say AMD can offer quad core Barcelona’s as an alternative, just as NVDA is saying there is ATI’s CrossFire as an alternative. (I own X1900XTX, X1900XT in C.F.)

My point is NVDA is pulling away from that standard. Today, buying and putting the best or fastest machine together is NOT what it used to be. NVDA has positioned itself, because of its great product and market position, to have the fastest machine on THEIR chipset. Skulltrail was a minor fix to try to appease Intel. It ain’t gonna work. You don’t deliberately make incompatible products; kick INTC in the teeth for two years, only to expect full cooperation and compatibility with CSI. In a pig’s ass you do. NVDA will get it, eventually, but oh are they going to have to some serious sucking, and make some serious concessions. (Like SLI?)

As a side note, I don’t know how the numbers would work in the long term end of things; I can only speak for myself. I, certainly, would have had two 8800 Ultra’s in my machine, instead of the C.F. setup. I am quite certain NVDA would have sold MORE graphic cards. I know I settled for what I got, and I didn’t like it a bit.

“(may be such as controlling the platform trend ...)”

You said it! They want exclusivity to the fastest high end machines, bar none, basically putting processor capabilities as a side line event. Even if you have the BEST chipset and processor, you still won’t have the fastest machine! They’ve limited my choices and that pisses me the @#!$ off! Why? I am building a new machine and I don’t like FBDIMMS (Skulltrail).

I’ve been waiting patiently for INTC to kick NVDA in the teeth.

It seems I am going to get my wish, real soon.

SPARKS

SPARKS said...

"they best start cozying up to Intel or else they will be relegated to fighting for scraps on AMD based CPU's, which last I checked favor the 'value' (read cheap) market and represent represent only ~25% of the overall market."

Lordy be, a truer word hath never been spoken! It’s like some cheap ass soap opera that I will be gleefully watching!

SPARKS

Anonymous said...

"I've been unable to find anything indicating that AMD is using Nickel Silicide."

FYI - when AMD claimed strain they were technically correct as they were using alternate stress techniques (I think at the time it was the SiN liners and/or SiN etch stop layer). What was not understood is that Intel was using embedded (and selective) SiGe and were the first company to put this into high volume manufacturing as best I know of. this was a significant breaktrhough in PMOS performance (thru enhanced hole mobility) and was subsequently implemented by IBM (and handed to AMD) one generation later.
As for NiSi, this also was a breakthrough as folks in the industry were attempting to do this for since as early as 180nm days (incl Intel) - the issue on this was largely new yield problems, which Intel finally overcame on 90nm and again IBM followed (and AMD purchase) on 65nm. Both of these gave very specific and quantifiable process performance in terms of IDsat and Ion/Ioff curves - as opposed to what still remains rather sketchy data on the benefits of SOI on nodes beyond 65nm - but hey AMD keeps touting SOI so it MUST be good right?

Scientia's background on the process-side of things is mindboggingly simple. He uses clockspeed as a measure of process performance which for anyone with a background is aware of, is a joke. He also argues that Pentium M on 90nm hid the issues... of course a counterview is that the Pentium 4 architectural deficiencies were highlighted by 90nm... there was nothing wrong with the technology it was simply a bad architecture choice; this is clear as the architecture was slightly better on 65nm, but still not very good. His choice of whether it is a bad architecture or bad process seems to vascillate depending on the argument he is trying to make.

It is also now amusing that he has come to grips that 45nm will not start at above (or even likely equal) to 65nm performance. This only strengthens the point that his comparison of how far AMD is behind Intel solely based on schedule is that much more absurd. As he now OPENLY ADMITS, it will take a couple of 'revisions' to catch up to 65nm performance.

But I suppose the next time he does a process technology schedule comparison he will once again naively use the AMD intro and say 'AMD is closing the gap, immersion litho, blah blah blah...', which is complete and utter crap as even now he admits it will be several iterations into it before it starts getting mature performance-wise (in my opinion ~9-12 months).

It is also now amusing that he states the specific technologies like strained silicon, low K are not important as the overall cost and performance. Funny thing is this is the same IDIOT who's been touting SOI (which, oh by the way adds ~10% to the finished wafer cost) and immersion litho (which, oh by the way, is more costly than a double exposure dry litho process) as examples of AMD's improvements in technology. And the specific cost and performance benefit of these would be? Oh, that's right, the great Dementia doesn't need andy ACTUAL DATA, it's just a requirement for those with a differing opinion.

Scientia - be a man and post on this board, or stop censoring posts on yours! And before you say why don't I just post on your board, I would, but the problem is even if something contains no personal attacks, if it disagrees with your assessment or show what an idiot you are when it comes to process knowledge, you will not post it!

Perhaps you can do a blog on "Ion power draw", you poser! Could you explain that expression again!

CHUMP!

Anonymous said...

You'll like this one sparks:

http://eclipse.sys-con.com/read/505602.htm
"Intel is off planning the launch of its six-core Dunnington microprocessor, a hex, if you will"

I wonder if they will consider a desktop version?

Of course as a "glued core" this will be one of those 'inelegant' solutions that performs well... likely to be yet another lucky break for Intel?!?

AMD's version of the hex core? it's called a 2P server with Barcies with a core that is not working that well... but snuck past that fantastic QA AMD has.

Simply looking at the 2P market - this would be 12 cores at a good clock speed - this should give an AMD 4P system a run for the money, even with an 'archaic' FSB.

Anonymous said...

Hey sparks why would Intel bother with SLI when it has crossfire licensed and works much better and more efficient and without the issues with multi display systems?
If Intel is indeed going after GPUs and multi GPUs it will for sure adopt Crossfire.

SLI has been dead in new features since its release; contrary to Ati crossfire that has already improved (thought revisions) about three times.

george said...

Because according to X-bit labs, among the multi-gpu users "Nvidia’s SLI technology is clearly more popular than ATI’s CrossFire. Steam hardware survey indicated that there are about 96% multi-GPU systmes with two GeForce chips and only around 3.9% - 4.0% machines that feature two Radeon GPUs."

Anonymous said...

So george what you are trying to say is that when Intel releases its own GPU it will use SLI which only works in Nvidia chipsets? That doesn’t make any sense.

george said...

Not exactly.

anonymous asked :
"...why would Intel bother with SLI when it has crossfire licensed..."

And I answered that Intel bothers with SLI because 96% of multi-gpu systems ARE SLI.


Intel's gpu (when and if it will be realesed) won't be compatible with SLI.

george said...

Unless u believe that Intel will manage to create a gpu that is faster than anything nvidia has to offer, which I consider impossible.

SPARKS said...

“Hey sparks why would Intel bother with SLI…….?”


Nah, I got to admit, the Nvidia 8800 Ultra, in SLI, will kick my 1st generation, X1900XTX C.F., setups ass down the stairs and out to the curb, no doubt. The new 38xx series leaves me unimpressed. It’s simply not a great performance increase from my current setup. NOT WORTH THE UPGRADE, DAMMIT!

That said, I’ve VERY happy with my BTM (before the merger) ATI cards. They still run everything well. I’ve had minor issues that were application specific, but have always been corrected with new driver revisions.

In fact, my wife and girls’ got daddy a Valentine’s gift this year, ‘CRYSIS’, (they know Daddy’s a bit odd). The store, clerk told them, “powerful machine…..Yada, Yada.” My wife knew better, and bought it. Anyway, it runs great, no slow downs, automatically selected at ‘medium’, and I am happily killing North Korean Communists @ 1280 x1024, native.

I think the current issues you refer to have recently evolved from the manufactures shoving new hardware out the door, and releasing immature drivers (read: untested in all apps). However, with the performance I’ve gotten over the past 2 years (!), I’ll never go back to a single card solution again.

It’s like having the ‘BFG 9000’ in your arsenal; you got it there when you need it. And, after two years, it still has a full charge!

As far as quad graphics solutions, if they can get ‘em to work, and DOUBLE my frame rates, fine, I’m in.

For now, the graphics market dynamics are very much in the air. I’ve got a decent setup. I’ll take a wait and see stance. Let’s see how my beloved INTEL will handle the current NVDA instigated graphic quagmire.

‘Walk softly and carry a big CSI, Q6600, two discrete cards, and Rail Gun.’

HOO YAA!

SPARKS

SPARKS said...

By the way, George (above) is pretty much on the money. Ultra Cards in SLI are absolutely insane.

(sigh) Oh how I wish.

SPARKS

Anonymous said...

intheknow,

Scientia copied over your post from this blog over to his and "responded" to it.

What a chicken s@*#. Why doesn't he come and reply here? Instead, he choses to reply in the forum where he has editorial control.

In another development, did you see George Ou's post on Nehalem performance projectors over AMD?

Leaked Intel Nehalem performance projections over AMD Shanghai

Looks like an AMD killer

Anonymous said...

Looks like Scientia is posting more delusions again, he is right up there taking data out of context to make a point that is incorrect but supports his point of view. What a dumb fuck


Its obvious why the P4 didn't scale at 90nm and again at 65nm. It had nothing to do with lack of innovation or bad process. The pipeline for architecture was too deep and managing that the required clock speeds led to too much power. That is why INTEL like AMD went to wider architecture and finally multi-cores. It could have scaled easily to 4+ GHZ but power was the mantra and thus higher frequencies were never released as what good is a 4GHZ, hot and not efficient processor worth. Since then C2D had been doing nicely on 65nm and the 2nd incarnation on 45nm should also scale nicely.

AMD of course is trying hard, but it doesn't have the money nor technology to compete and thus you see the result. It is falling furhther and further behind.

Of course ATI was a bad purchase, how can you piss away money and management focus and take the eye off the CPU. Like INTEL AMD fucked up. Unlike INTEL which has money and technology to recovery AMD has neither.

AMD is finished...

Keep it up Scientia but you don't know squat. You are right up there with your buddy Sharikou, laughing stocks of the internet

InTheKnow said...

Instead, he choses to reply in the forum where he has editorial control.

Which is why I don't post there. Never argue with a radio talk show host. He will always get in the last word.

I'll just let his "response" stand in his own forum. I considered responding, but I'm not interested in trying to conduct a discussion across 2 forums.

And where Scientia is concerned, I'm of the opinion that the rhyme I learned long ago applies all too well.

"A man convinced against his will,
is of the same opinion still."

Ho Ho said...

Some news about 45nm Cell CPU:
http://realworldtech.com/page.cfm?ArticleID=RWT022508002434

Most important was this:
"No High-K gate-oxide or Metal-Gate electrode in the 45 nm SOI process used by the 45 nm CELL processor."

I'd say we can safely say that AMD will not use either of those either on 45nm.

Giant said...

Intel's 130nm process yielded a maximum of 3.46GHz processor. That's faster than any AMD 90nm or 65nm processor. Therefore, I conclude that Intel's 130nm process is far superior to AMD's 65nm process. In fact, Intel's top clockspeed at 45nm is 3.2GHz. This means that 130nm for Intel is better than 45nm.

Now stepping back into the real world....


Leaked Intel Nehalem performance projections over AMD Shanghai


There's no indication that Shanghai will launch at 2.8GHz. Indeed, it's almost a certainty that AMD's 45nm processors will launch at lower clockspeeds than their best 65nm. This has been true for AMD when going from 130nm to 90nm and going from 90nm to 65nm. Intel's results are also giving Shanghai a very healthy IPC boost over Barcelona. I'd suggest that Intel is displaying the absolute best case scenario for AMD. Unforunately for them, I don't see this happening. I see Shanghai at 2.4 or 2.6GHz, and IPC increased in the range of 5 - 10% due to the larger L3 cache and the minor tweaks AMD is making to the core.

BTW Sparks, you were eager to see 4.5GHz on the E8400 - and speculated that some H2O might just do the trick. I got their on air. I replaced my CPU hsf with a Thermalright Ultra 120 Extreme coupled with a Noctua 120mm fan for effective but quiet cooling. On the northbridge I added a Silenx 40mm fan to the ASUS heatpipe cooler. With this improved cooling in place I have no troubles running 4.5GHz 24/7 on the P5B Deluxe.

Anonymous said...

"I'd say we can safely say that AMD will not use either of those either on 45nm."

This was a safe assumption the day AMD said they are looking into/keeping open the possibility of doing high K in the late stages of 45nm. It was only people like Scientia, who don't understand the intricacies of implementing this magnitude of a process change, who thought AMD could just slam it into a later 45nm revision and took the AMD statement as a plan, instead of a PR spin.

That said, I would not discount the potential for some AMD grandstanding by putting out some low volume part with high K to say look we could have done it too...(but customers weren't demanding it!) However, the only way this goes to decent volume is for extremely low clockspeed parts (for ultra low voltage application) or if 32nm completely falls apart.

Unfortunately the press on the web, has simply become a typist for most firms. Instead of asking do these comments seem reasonable, they ask how quickly can we post this up on the web. Welcome to the NY Times era of journalism where innuendo and opinion is a news story, damn the actual facts and trying to get a complete story.

SPARKS said...

“With this improved cooling in place I have no troubles running 4.5GHz 24/7 on the P5B Deluxe.”

There ya go, the new overclocking darling of the enthusiast world. I damned well knew it. INTC was ready to clock these bad boys no mater what AMD released. No one is ever going to tell me INTC didn’t sandbag the current 45nM tech. Giant, I am absolutely busting that you are having all the fun, while I wait like a goddamned dog in heat for ‘The New Brothers Blue’.

As a side note, with all the horseshit mentioned above concerning Dementia and his wild eyed, half assed analysis, I wonder how he factors his ‘scaling’ theory on this 4.5 GHz bad boy, bread and butter chip, out of a retail box.

Blaaaa!!!-----WRONG AGAIN!

By the way all, here is a nice link on how well AMD is scaling their new FAB’s and fabrication technology. What a joke. From what I’ve learned from this site, “intricacies” in process and fabrication is a MAJOR understatement, big time!

Here is conspiracy theory at its finest. IBM, AMD, Chartered, Et al, are all rallying their forces against INTC to pull AMD’s balls out of the fire.

Wait, I think I see Bigfoot and a couple of ‘Greys’ ready to take over the human race, right outside my window!!!

http://www.chinapost.com.tw/business
/2008/02/23/144164/AMD-may.htm


SPARKS

InTheKnow said...

It is also now amusing that he [Scientia] states the specific technologies like strained silicon, low K are not important as the overall cost and performance.

That is true up to a certain point. I don't buy a processor, because it has strained Si or High-K/Metal Gate. I buy it for cost and performance.

But the reality is that it is strained Si and High-K/Metal Gates combined with a micro-architecture that determine the cost and performance. So in an indirect fashion, it is exactly what I care about.

Nehalem should be very interesting because it will be Intel's first processor designed for their 45nm process. Penryn may have been tweaked a bit, but it is still an architecture that was fundamentally designed for their 65nm process.

SPARKS said...

In The Know, here is a very premature preview of Nehalems peformance. It's kind of nebulous to me, I can, however, read a bar chart. It looks pretty stong for a probably untweeked pre-release item.

SPARKS

http://blogs.zdnet.com/Ou/?p=1025

Anonymous said...

Sparks that info has been floating around for a little bit now (INQ is now attributing it to an accidental release via Sun).

I think the foils are indeed real, but much like the K10 "projections" this should be considered dubious until actual demos are conducted. Of course the Intel claims recently have been backed up, but much like AMD, any claim should be taken with a grain of salt. I also would like to see some actual application benchmarks, while Spec is interesting, I don't run spec on my desktop daily! And if you like to mess around like (ahem....AMD) you can creatively pick rate, base, peak, FP, INT, clock for clock, per donut consumed on the 3rd Wednesday of the month benchmarks...

That said I suspect within the next 3-6 months we will see something...and I suspect it will be good. I will also say we will likely not see much until 2009, with a possible token server part or two in Q4'08. Given AMD's roadmap this will not really matter.

Anonymous said...

"But the reality is that it is strained Si and High-K/Metal Gates combined with a micro-architecture that determine the cost and performance."

So sad...let me point out the error of your ways. Intel's performance is better because they got lucky! And it just happens to occure on virtually every technology node. Much like poker, when you say wow that person catches card CONSISTENTLY - you have to start to wonder if it really is luck (or the fish will say it's just luck while continuing to bleed money)

The problem is the 'we're catching up/closing the gap' mentality, the 'SOI is the end all', immersion litho 'it doesn't get any more cutting edge than that'... process performance does matter (as you say) and what is most important is INTEGRATED PERFORMANCE, which is why IBM now publishes and licenses while doing a little manufacturing on the side. Cool invention/research - easy to publish' putting it into manufacturing and getting integrated performance - not so easy. See the street littered with IBM 'breakthroughs' which were published but never saw the light of day, or came a generation or two or three after projections.

The problem is Dementia wants it both ways - he says process is not critical (to use AMD words, people don't buy nm), yet spends a lot of time trying to convince himself and people without a background in manufacturing that AMD is closing the gap... It's about cost and performance yet the only thing he focuses on is launch date introduction (by the way he continues to compare Intel PRODUCT AVAILABLE FOR PURCHASE to AMD "WELL, IT'S SHIIPPING TO OEM's").

Actually I'm wrong there he also presents the argument of clockspeed being a good metric of process performance - which is always a good thing when comparing 2 different architecture while managing to ignore cost, ignore time to market, ignore power, ignoring yield, ignore manufacturability... but hey he seems to be well schooled in this area!

InTheKnow said...

I said...
Nehalem should be very interesting because it will be Intel's first processor designed for their 45nm process.

But this isn't completely accurate. Silverthorne/Diamondville will be the first processors designed for Intel's 45nm process. But these are aimed at a totally different class of machines, so there will be no real comparison.

I've seen a number of articles now about Silverthorne (and Isaiah from Via as well), and it looks like Silverthorne will be a bit disappointing from what has been written. Of course I'm making this claim without seeing any benchmarks, so the press (and I) could be all ate up.

But the general consensus seems to be that Silverthorne will be an okay first of a kind product for Intel, but will lag behind the ARM and VIA offerings. Everyone seems to be looking forward to Morestown as Intel's first fully competitive processor in this space.

I also think that AMD's failure to be seen moving aggressively into this space is a big mistake. With such small processors, it has the potential to give good margins on 300mm wafers. And the potential demand is huge compared to desktop and server.

SPARKS said...

Guru, I want to throw my guts up. According to this article, AMD is going to indeed build a fab in NYS! (GROWN, GURGLE, CHUCK! I JUST PAID FIVE GRAND IN STATE INCOME TAXES!!!!!).

ME, an INTC shareholder am subsidizing AMD’s debt!!!!!! Where the hell are they going to get an additional 2B! to build this thing? Fuck’en A bubba!!!! Something’s going on here! The EU and N.Y.S. must think they have a pretty strong case against INTC, as they are both subsidizing poor beaten up little AMD.

Local and International Governments subsidizing, publicly held corporations, with Lawyers and Diplomats as tactical henchmen! So much for fair competition, what a stinking line of crap

Then there is a STRONG IBM presence here in NY, I’ll bet dollars to donuts that IBM will be a player in the N.Y. deal! The whole western world is fighting INTC’s complete market dominance! This is GOSPLE!

“Tatallia is a pimp! Tatallia (AMD) could have never out fought Santino. It wasn’t until this very day, did I realize it was Barzini (IBM) all along.”

http://www.tgdaily.com/content/view/36204/118/


SPARKS

SPARKS said...

........AND there is this!

http://albany.bizjournals.com
/albany/stories/2008/02/25/daily17.html

SPARKS

Anonymous said...

Looks like our favourite clueless fanboi Dementia got called out by George Ou over at AMDZone:

http://www.amdzone.com/phpbb3/viewtopic.php?f=52&t=135218&st=0&sk=t&sd=a

Re: Nahalem SPEC* numbers
by scientia on Mon Feb 25, 2008 4:30 am

I read Ou's article and naturally he kisses Intel's ass good and properly. That is, instead of the screaming fit that he threw when AMD used simulated numbers he instead happily takes Intel's simulated numbers as gospel. Having a double standard is pretty much the definition of being a fanboy.

The other points that Ou is apparently too stupid to mention is that Intel lists neither clock speed nor the number of cores for Nehalem.


Dementia then goes on to speculate on the probability of Intel's # of cores for the posted Nehalem performance chart, and as somebody else pointed out, his numbers don't even add up to 100%.

However, George Ou himself then replied: I'll probably be banned here after my first post just because of who I am, but I'm going to post a comment here since people have attacked me without giving a reason.

Now Scientia, I see you're up to your usual eloquent and well spoken self.


Of course, Dementia doesn't believe it's the real George Ou, probably because the real Ou had the balls to post on an AMD fanboi site whereas Dementia is too timid to post anywhere under his own name except in his tiny safe puddles and Dementia is ashamed of the fact.

Makes for some amusing if unenlightening entertainment..

Anonymous said...

You guys should check out the latest post from our favorite AMD rah rah who has gone down the path of sharikouism.

Our silly AMD sucker took all of AMd's executive's words as some sort of fact from god.

Is this guy a retard or what?

"You have to separate yield and speed; those two things don't correlate"

Is that spin or what. What good is a functional die if it don't run a speed? I learned early on that Yield without speed is useless and speed without yield is also useless. As an engineer and a business man you sell products that work and they need to work at the stated performance goal. Any moron who says he has a manufacturing process that has good yield but that at the same time the speed isn't there, but don't worry we make lots of perfectly functional products, people just aren't interested in them or we hvae to sell them for cheap because they don't want to pay for them is someone you don't want running a business with the goal of making money or staying in business for long.

There are many reasons you have poor yield. You have a equipment or process that is dirty, you have immature process that results in process variation that cause functional fails or speed fails. It really matters not, the bottom line is if you technology does't produce chips at speed then the yield is low. To somehow claim the process is healthy and all you need to do is tune the design. Then in my mind you have a bad process or bad designers or possible both.

For example if you go to TSMC they offer you lots of design resources. They give you transistor models, interconnect models, design rules, and DFM guidelines. You take those and put them into your design tools to insure your logic meets timing, has margin to tolerate the multitude of variations. Then you tape it out and you expect to get prototypes back that work at speed. In todays complext CPU you expect some bugs to escape your pre silicon validation to miss capturing some subtle design and process interaction. But IBM aren't they the best at process and AMD arent' they the best at design? Now imagine out comes your chip and it works at some slow frequency but at speed it 0 yields. Who's fault is it? Designer who didn't tune his part? Or is it the fab and process who can't suport a design that was designed to issued guidelines. AMD got a broken design or does IBM have a broken process?

The end results say it all, there are no high speed 65nm parts from AMD. Talk is cheap, ship the product and you don't worry about FUD. Today INTEL is shipping 45nm parts already. Already there are writeups of overclocking of those parts. Sure 45nm parts are in short supply but I expect by middle of next year with two fabs up and two more coming on line parts there will be many parts. Today AMD has nothing to speak of on 65nm. And its more funny to believe these same clowns are claiming that they can deliver 45nm on time. They can't even get 65nm right how are they going to get an even more complex 45nm process with more senstive process to work faster.

InTheKnow said...

This from the article
AMD Forges Ahead in New Chip Technology
right here on robo's blog.

According to AMD, the chip industry is expected to begin producing 22-nanometer chips in 2016.

I really hope this is a misprint. We reached 45nm in '07 and are slated for 32nm in 09. That would mean that AMD only expects to need 17 years to reach 22nm if the quote is accurate.

Of course even more odd is that they demoed EULV in the back end where the line sizes are larger and ELUV shouldn't be needed any time soon.

Anonymous said...

I think you mean 7 years (not 17), but either way the timeline doesn't makes sense.... of course looking at the bio of the author he has a BS in history, so he appear imminently qualified to discuss these matters.

Anonymous said...

Sparks - ignore the TG crap... the devil is in the details - they are talking about going ahead with permitting and clearing the land, this is fairly low cost and is probably a smart thing to do in case another sugar daddy comes along. They are also talking about a permit to start as early as Jan09... which would be best case... now look at how long it took from breaking ground in Dresden to actual wafer outs. AMD will have plenty of opportunity to pull the plug on this, likely thru 2010 even if they proceed... I forget when the option will expire on this subsidy but I think it requires some sort of decision in 2008 (maybe summer?)

What is really amusing in that article: 'It seems that design of the Dresden complex was so successful (AMD has room to build up to five Fabs in Dresden) that AMD plans to do the same thing in NY state...'

and goes on to talk about the potential to do up to 3 cleanrooms (essentially 3 fabs on one site)... apparently Dresden was so successful at this? How many cleanroooms are there on that site? How many WOKRING CLEANROOMS does Intel have on their Oregon site that are connected?

While it is good to plan for success...let's get real here... if Dresden can do 5 cleanrooms, do they really need 3 more in NY? I mean this is a bit overkill no? So they basically can build 3 more fabs in Dresden (assuming they get around to doing something with F30/38)... the only reason NY is in the picture is because of the 1.2Bil theft from NY taxpayers. Otherwise why would they not continue to build out the "highly sucessful" design in Dresden where they already have infrastructure in place - apparently the design in Dresden is so good they need to got to NY after building out 20-40% of Dresden's potential capacity. I find it amusing this from coming from a state which has a senator running for president, bashing the coporate tax breaks and the evil corporations. I must have missed the part where she was outraged by this deal, occuring in her 'backyard'...

This appears to be a hedge in case they find another sucker, err...investor, though not sure why they wouldn't use any new money toward finishing F38 conversion/ramp. Oh that's right the payola from Germany is over.

InTheKnow said...

I think you mean 7 years (not 17)

You're quite right. And to think that I'm paid for my math skills among other things. :(

InTheKnow said...

'It seems that design of the Dresden complex was so successful (AMD has room to build up to five Fabs in Dresden) that AMD plans to do the same thing in NY state...'

To further put this in perspective, look at Intel. I believe they will have 8 300mm fabs when they are done with their build out.

Intel is pushing for 450mm wafers. When this eventually happens (and it will happen despite all the resistance) Intel will need just under 4 fabs to generate the same output as their 8 300mm fabs.

Unless Intel completely folds, I don't see AMD ever needing more than one campus after they eventually go to 450mm wafers.

My point is building a fab in NY would be very short sighted on AMD's part. They don't need the capacity now, and are unlikely to need it in the future after the move to 450mm wafers.

Anonymous said...

Rumor: amd fab to bankrolled by middle east courtesy of The Inq

InTheKnow said...

Phil Hester said...
And so, getting higher speed grades really requires kind of tunning if you will the design points, looking at how the individual transistors and the critical path are specified and work and mapping that onto the technology. (emphasis added)

I could be wrong here, but when you start talking about individual transistors, I start thinking about CTI. Reading between the lines here, it sounds like debugging the design (the reference to speed paths) and CTI are interacting in a way that is slowing down the "tuning" process.

This is something that Intel doesn't have to deal with. The transistor characteristics are laid out well in advance and the process is tuned to deliver the expected performance before it ever moves into production.

Ho Ho said...

Another gem from Scientia from amdzone:

"I never distort facts"

Anonymous said...

I'm not too sure about that Phil Hester transistor quote - and would take it for a 'generalization'. CTI is not tuning anything on an individual basis - you simply cannot do this as fab processes are WAFER based so changing something on the equipment will effect the entire wafer (or a substantial portion of it). There are a few potential process steps that 'raster' over the wafer but again, this is still done on a relatively large area basis and not able to pick out an individual or even a small group of transistors.

Now you can tune individual transistors by changing the size and layout - but this means new tapeouts, not on the fly fab process changes/adjustments. Amd you can have issue with specific speed paths.... but if you need to change a specific transistor you are doing it at the mask stage.

Intel does seem to do a better job at designing in margin (via the restrictive design rule process), the more margin you design in the less likely you are to fall off a cliff (and fall several speed and/or power bins). I think one aspect of this is the overclockability of the recent chips - you can see headroom in there.

You can see the impact of fab manufacturing variability in the variability of OC for a given product. A chip manufacturer has a couple of options - design things such that the chip barely meets targets, this likely means bad binsplits (as any variation will cause the chip to miss the process window) and limited overclockability. If you set the bar low, you are potentially leaving a speed bin on the table, but your splits are much better and the chips should OC well. I think this is the regime Intel is in right now - if/when AMD pushed them, they will likely push the envelop on the process window which will mean another speed bin or two, but it will come at the cost of binsplits and will probably mean no change in the OC-ability of the chip, despite the higher bin.

I believe (though have no direct data) that AMD's initial issues with K10 is that they are pushing very close to what their fab process limits are.

This is something that easily can be missed when running the handful of early validation lots as tools can be dialed in and setup carefully; however when you hit higher volumes you start introducing tool to tool variation and wafer to wafer variation and you may fall out of the process window if it is small. I expect AMD really did have decent samples early on (and thus the early INQ and other rumor site reports), but ran into issues when trying to scale this up. I still think the whole TLB issue is not at all related to the clockspeed issues and is simply a convenient scapegoat.

All this is speculation on my part...

Anonymous said...

Well, Dementia apparently has latched onto that same Hester interview and, as typical, has completely MISINTERPRETED IT!

"So, again according to AMD, their 65nm process is not broken, is not behind, and has never had poor yields."

All Hester said was they were not having yield issues... of course Dementia twists this into they are not behind and process is not broken. Is it possible to have good yield with really bad power characteristics? Is it possible to have good yield and low binsplits? If I had perfect yield, with all the chips coming out at 1.0GHz and 400Watts, would that be healthy/not broken? All Hester said was that yields were fine (neglecting the fact that we have no idea what 'fine' is), he provided no data, provided no comments on actual binsplits and made no comments about process 'health'.

The fact that he is trying to draw a distinction between speed and yield is all you need to know... this is like calling Ford's auto line healthy because all the cars that come off it start and the wheels don't fall off. You just need to distinguish between ability to start the car with things like acceleration, fuel mileage, functionality... but hey according to Dementia the fact that they all start would imply 'health'

Of course Dementia swalllows the garbage of tuning transistors yet ignores the fact that a SHRINK OF A KNOWN, PROVEN ARCHITECTURE (K8), still can't match the speeds on 65nm that they were able to achieve on 90nm.

And the new 'nugget'..... well the clockspeed ramp-rates are similar. It's called perspective (or lack thereof), if you start really low and ramp the speeds up of course that looks good on paper... but look at the starting (reference) point. If Intel churned out 2.0GHz processors on 45nm and quickly ramped it to 2.8GHz, that would be an extremely healthy process by Dementia's definitions as yields are good and the ramp of clockspeeds is good. I would call this less than healthy as the starting point is so low. Keep in mind AMD is now over a year into a typical 2 year tech node cycle, and they still can't even match clockspeed of their previous generation on the same K8 architecture... am I supposed to believe this is by CHOICE and is not process related? Or perhaps AMD was unable to perform a simple design shrink? This then gets re-inforced on K10, which starts out 2-3 speed bins below expectations and 6-9months later there is no clear roadmap on whether they will get beyond what they originally expected to launch he product at. This is healthy?

He just doesn't get it... I don't know why he feels the need to spin everything in a positive light. Good yield, by AMD's definition means a good # of functional die (and keep in mind you have tri-core probably artificially boosting the yield #'s). A process is healthy when it has good BINSPLITS! Not just working/not working. This obvious distinction just continues to reinforce Dementia's complete lack of a manufacturing background.

SPARKS said...

If I may, getting back to the subject of Doc’s post, the EU gangsters, Zig Heil !, has just found Microsoft guilty, and subsequently fined them a cool 1.2B. Things do not bode well for INTC as the EU can issue lawsuits and fines unchecked by any governing body.

Incidentally, does anyone know who collects the bonanza, where it goes, and how it’s distributed?

OK, back to process. Guru, your “speculations” are worth their weight in gold. Further, I have been reading about ‘In The Knows’ Extreme Ultraviolet process (EUV?), they say it’s easy to do on a single layer, however, the “pathways” are problem because of the interconnects between layers don’t work very well.

Additionally, the angle of, what I see as projection (?), is limited to roughly 9 degrees during exposure. They say it's good down to 22nM. But, they also say they have been jerking around since ’99 with this thing.

I’m sure there are other issues, I’ll never know (or understand) like the special function, dedicated tools, for instance. However, is there any substance this technology they have been ‘breaking through’ for ten years?

SPARKS

Anonymous said...

"However, is there any substance this technology they have been ‘breaking through’ for ten years"

I'm skeptical, especially if you are referring to the IBM announcement. I have no doubt the claim is real, but as always the question will be, is it manufacturable? To put things in perspective I was hired in the industry ~12 years ago by someone working on x-ray litho (which is pretty much the same as EUV).

From what I understand (and litho is not my area of expertise) is that at least a 10-100X improvement is needed in the light source to have reasonable throughputs, there are still issues with mask degradation (these are reflective masks that degrade over time as they are exposed to high energy radiation as opposed to the current masks that rely on 193nm transmission), there are the issues that always exist with new resists and the projected costs of these tools are obscene! The low end appears to be $40mil/tool with some projecting ~$100mil PER TOOL by the time this thing gets to manufacturing. If you have the typical 4 critical passes that need these tools, you are talking ~4 tools for a 20KWSPM Fab, so potentially ~400Mil for just these tools!

Another key issue is IBM/AMD alone can't drive this - they are peanuts in the grand scheme of things in terms of capital equipment purchases (compared to Samsung, Intel, TSMC). They are in a bit of a catch-22; if this is an exclusive solution for IBM's fab club, would the litho equipment suppliers do this for what would be a very small market? If IBM licenses it to the suppliers (which is the most likely case), then they stand a chance of getting the support.

My best guess is more creative solutions are found to extend immersion litho longer than expected (you can do double exposure at 32nm and possibly 22nm). There is also potential for improvements in the fluid used which could enable a higher NA and enable additional extendability. The earliest I see EUV is the 15nm node (45nm --> 32nm --> 22nm --> 15nm). Putting things in perspective again this is ~2014-ish at the earliest.

So how critical is this announcement? In my view, not very; another nice PR exercise.

Anonymous said...

EU double standard.

The EU is so willing to go after MS and INTEL for what is simply hard nose competition. Both companies hold the upper hand and clearly look to leverage their gorilla position to maximize profits. Does management sanction what it knows is illegal? I don't think Gates, Balmer, Barret nor Otellini are that stupid. Do they look to go to the limit of the law, most sure.

Now lets look at that compared to a European based company like Siemens. Here is a huge European conglorate that was caught outright breaking the law using bribes both within the EU and outside. The scope and amount of the bribes were huge as were the contracts in question the hundreds of millions of Euros.

And what was the consequence? It was a few tens of millions Euros.

Double standard? Local company caught outright breaking the law, fined tens of millions. Foreign company being very competitive to the very limit of the law? Fines of billions.

All they got is their history and culture but business and innovation is going to pass them by with this kind of anti-competitive BS and favortism.

Ho Ho said...

sparks
"Things do not bode well for INTC as the EU can issue lawsuits and fines unchecked by any governing body."

Well, what about all those tens of EU countries?


"And what was the consequence? It was a few tens of millions Euros."

Actually it was about 400 million euros. Combinining all the fined companies together it was 750M €. MS was fined for 1.3B$ or around 870M€. Difference isn't all that big.

So are we still talking about double standards?

Ho Ho said...

Oh, and a small little facts I just was reminded: MS just burned $1B on their buggy XB360 they didn't bother to test properly. Before that they lost $4B on the original XB sales. Now that dollar has dropped all-time lowest that $1.3B is peanuts.

Ho Ho said...

And before anyone is asking why is MS being fined and not any other OS manufacturers, read this and think about it a little.

Anonymous said...

" don't think Gates, Balmer, Barret nor Otellini are that stupid."

Then you are clueless. These same tactics were used by Coke. After Pepsi sued Coke the two reached an agreement and then used the tactics jointly. This was done by Hallmark as well. Using monopoly tactics that go beyond the law is not limited to MS or Intel. The willingness of companies to go beyond the law is not related to stupidity but simply the willingness of governments to enforce existing laws. If enforcement is lax then they go further; if it is tight then they back off.

This is probably less of a witch hunt against MS and Intel and probably just more of a shift in attitude about enforcement.

Axel said...

Anonymous

The willingness of companies to go beyond the law is not related to stupidity but simply the willingness of governments to enforce existing laws.

This is all idle pointless speculation if you don't provide links to proof of your assertions, and yes the burden is on you. It's like claiming that humans never landed on the moon and that all the pictures were doctored.

Anonymous said...

SOI... the wave of the future?

"Soitec takes action to resume growth"
http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=SKYJ0KLFYFHQGQSNDLRSKHSCJUNN2JVN?articleID=206900778

"Actual demand from the company's two main customers, namely Advanced Micro Devices, Inc. and IBM Corp., that is covered by the contractual minimum quantities is running behind schedule by around 14 percent."

Anonymous said...


Another gem from Scientia from amdzone:

"I never distort facts"



ROFL...

SPARKS said...

“the projected costs of these tools are obscene! The low end appears to be $40mil/tool with some projecting ~$100mil PER TOOL by the time this thing gets to manufacturing. If you have the typical 4 critical passes that need these tools, you are talking ~4 tools for a 20KWSPM Fab, so potentially ~400Mil for just these tools!”

Ok, I was correct about the specialized tooling. Where the hell are they going to get that kind of money to gamble on an entirely new process, yet again.

“they are peanuts in the grand scheme of things in terms of capital equipment purchases (compared to Samsung, Intel, TSMC)”

Guru, I laughed like hell when I read that. Pompous IBM, and suck up AMD, they make a perfect ‘Mutt and Jeff’ team.

“There is also potential for improvements in the fluid used which could enable a higher NA and enable additional extendability.”

So that means INTC is not using ultra pure H2O. (The only thing I could find on Immersion). So this means, by default, they are using something other than water. How creative can you get with water? Other substances would need to be basically inert to the resist, the previous layers, and the tool, no?

Finally, what is the problem with Immersion, INTC has clearly (ultra pure water, forgive the pun), demonstrated that the process works quite well. (QX9770 where art thou?) So why all the Nay-Sayers and detractors? In my line of work, if something works, you don’t touch it. If it breaks, we’ll fix it.

INTC makes BILLIONS on Immersion and the idiots say it’s a bad process. You've got Billions of successes; as opposed to BILLIONS of losses for hocus pocus EUV! Besides, if any one reels it in, my money is on INTC.

Sorry, I don’t get it.

SPARKS

SPARKS said...

“So are we still talking about double standards?”

Ho Ho, so what are you trying to say? Whether or not they collect money from INTC, MS, or the Gestapo Lampshade Company, is inconsequential? Who and what gave them the self-appointed authority to be the world’s business police?
Are you justifying their actions in free world market? Who and what determines their criteria? Especially in view of arrogant, pompous statements like this:


“This should be a signal to the outside world, and in particular to Microsoft, that we stick to our line,”


Zeig Heil!


You addressed me, however, your position on the mater was unclear. What say you?

http://www.nytimes.com/2008/02/28
/business/worldbusiness/28
msoft.html?_r=2
&oref=slogin&oref=slogin

SPARKS

SPARKS said...

“This is probably less of a witch hunt against MS and Intel and probably just more of a shift in attitude about enforcement.”

Horseshit. Clueless? Listen, I know some people in Brooklyn, if you want to do business in their neighborhood, “it’s gonna cost ya”, especially if you’re the only game in town. It’s called ‘VIG’.

Capieso, si?

That’s what this is about, pal.

SPARKS

Anonymous said...

"So that means INTC is not using ultra pure H2O. (The only thing I could find on Immersion)."

I don't know - I would suspect they would start with H20 if that worked (since they are not doing it on 45nm, it is unclear if H20 immersion will work or H20 double exposure, or 'high NA' fluid single exposure will be needed for 32nm - some have suggested 32nm will require double exposure even with immersion. My intended point was that they're is some potential improvement roadmap for immersion litho, despite many saying it is only good down to 32nm (funny there was an article on EEtimes/Silicon Strategies page on EUV just today....)

As for EUV and gambling - a lot of work can be done in litho on non-integrated / non-production tools to validate the optics/proof of concept / work on resists and other issues. Eventually you have to do it on a production worthy tool which can introduce some subtle challenges, but a lot of work can be done on 'alpha' or 'pre-alpha' tools which would obviously be less expensive. I imagine they're are several IC manuufacturers with alpha type setups inhouse for some time now (Intel among them)

There is nothing wrong with immersion, the tools are more expensive and less mature, the process adds some new complexities (as you might imagine things like control of the thickness of the immersion layer is critical as you step across the wafer), but you are still printing with a 193nm source in much the same manner as a dry litho tool. Though I guess it seems better if you tout it up as some sort of major breakthrough...all you are doing is putting a thin layer of fluid between the mask and the wafer when irradiating the pattern (the entire wafer is not 'immersed', just the area being patterned)

Intel chose to go the conservative route with double exposure, it adds some complexity, but uses proven tooling and the infrastructure is the same as previous generations... if AMD could push double exposure to 45nm I don't see why they wouldn't have. That's not to say there are some challenges with double exposure as well (reg/overlay budget is tighter).

As for Intel making billions - I think you mean dry litho double exposure, Intel chose not to go the immersion route on 45nm. The 'nay-sayers' seem to think newer = better, if I could re-use the same equipment for 10 generations with similar cost and technical performance and faster time to market, I would take that in a heartbeat - that's the difference between a manufacturing view and a research view. It just doesn't make as good press as something 'cool' and new.

InTheKnow said...

So that means INTC is not using ultra pure H2O. (The only thing I could find on Immersion). So this means, by default, they are using something other than water. How creative can you get with water? Other substances would need to be basically inert to the resist, the previous layers, and the tool, no?

I'll preface my remarks by saying that I have made tremendous efforts in my career to stay away from litho processes, so I am no expert.

But from what I've gathered, immersion litho improves on conventional litho by passing the light through a thin layer of ultra pure water. This works because water has a different index of refraction (how much it bends light) than air. You can change the properties of the water somewhat by adding very small amounts of selected materials, such as a surfactant (soap if you will) or a number of other substances.

Another area where I've heard there are issues with immersion litho is with microscopic air bubbles entrained in the water. These cause distortions in the image and at the dimensions we are talking, it is enough to cause problems.

Finally, what is the problem with Immersion, INTC has clearly (ultra pure water, forgive the pun), demonstrated that the process works quite well.

I'm not sure what you are asking here. Intel won't move to immersion litho until 32nm, which isn't in production yet.

If you are asking what is wrong with conventional litho, I think one simple fact will put the problem in perspective. The features that are being patterned are 1/5th the size of the wavelength of the light being used.

Just imagine using tools 5 times the size you need to build anything, and you can envision the efforts that must have gone into getting the process to work.

And for the record, Intel has been working on EUV (I have no idea where I got the "L" from the other night) for a long time. Something will have to be done about the wavelength issue mentioned above in the not too distant future and EUV is one of those options.

Anonymous said...

"It’s called ‘VIG’."

#^&@*! hilarious! Careful or I will have to send Vinnie and Tony after you!

Oh and by the way the money doesn't go to EITHER the consumers or AMD (or in MS's case, their competitors)... so ask yourself who benefits from the fine - the lawyers who are racking up the billable hours and the government(s) collecting the money.

What's funny is a case could potentially be made that these fines in the end will end up hurting people as the money coming out of the companies pockets comes from the revenue collected on sales or means less dividends and/or lower share price appreciation to the stakeholders. I wonder how many pension plans and retirement funds have these companies as part of the portfolio?

So the question you have to ask yourself is... is the EU going to more effectively use the fine money or would the company that was fined make more efficient use of it? If you live in the US, I'd just need to ask if you are a liberal or conservative.

Anonymous said...

"This is probably less of a witch hunt against MS and Intel and probably just more of a shift in attitude about enforcement."

OK, let's assume everything the EU alleges is 100% correct for a second. So what? I can see how this would hurt another American company (AMD), but how was the EU consumer injured - isn't that who the EU is supposed to be representing?

Specifically how much did they overpay for CPU's? Take that number multiply it by 3...give the money back, with a small bonus to the consumers who allegedly overpaid and use the rest to cover the ridiculous costs incuurred in performing this witchhunt, um... investigation.

Now is that what is going to happen to the money? OF COURSE NOT! Did the EU consumers overpay because of the alleged tactics? Who know?!? Maybe they even paid less as the companies getting the rebates could pass them on to the consumer. OR... maybe the EU should go after the people accepting the rebates? Weren't they also benefiting from the alleged activity?

Was Intel right? Who knows, if what is alleged is true, probably not. But is the EU fine really going to help the EU consumers? What about the EU distributors who were more than happy to collect the rebates? Should they be penalized too or are they just innocent pawns in all of this?

Whatever the outcome there is a ton of hypocracy and social engineering by the EU in all of this.

Ho Ho said...

sparks
"Are you justifying their actions in free world market?"

Are you justifying their (MS) actions in the free world market? Who else should play the police and see that global corporations play nice? Before Bush came to power US could be it but not any more. Remember, they almost divided MS into three different parts but they abandoned the plan quicly after the new president.


"Who and what determines their criteria?"

International laws, perhaps?


Btw, why do you think people have subscribed to NYT? I certainly am not.




"Oh and by the way the money doesn't go to EITHER the consumers or AMD"

The money EU gets from fines goes to EU budget. All EU member countries have to pay X€ membership fee (given back to them as grants). If some big company pays Y€ fine then members have to pay (X-Y)€. So basically EU citizens don't have to pay as much taxes to pay the membership fee as big and monopolistic companies pay it for them :)


"I can see how this would hurt another American company (AMD), but how was the EU consumer injured - isn't that who the EU is supposed to be representing?"

Are you saying you don't understand how monopolistic market can hurt consumers? The Inte-AMD story was kind of shady a few years ago but current (and previous) MS things most certainly are not.

SPARKS said...

"As for Intel making billions - I think you mean dry litho double exposure, Intel chose not to go the immersion route on 45nm."

Sorry, I stand corrected. Thankyou, I'l checkout the dry process.

SPARKS

Anonymous said...

"The money EU gets from fines goes to EU budget. All EU member countries have to pay X€ membership fee (given back to them as grants). If some big company pays Y€ fine then members have to pay (X-Y)€. So basically EU citizens don't have to pay as much taxes to pay the membership fee as big and monopolistic companies pay it for them :)"

This is a ridiculous argument - basically the EU customers who were 'injured' (financially) through the monopoly have their lost money redistributed throughout the entire EU? Actually worse as the EU governments and the lwayers, take their, tio use Spark's words "VIG" off the top to cover expenses. Sounds more like redistribution of wealth.

"Are you saying you don't understand how monopolistic market can hurt consumers?"

I'm saying the EU should be responsible for definining SPECIFICALLY how the EU consumer was hurt by the monopoly. Isn't that the point or is the EU saying that no monopoly is allowed to exist. I agree in the MS case it is a bit closer to clear, but I fail to see how the EU consumer is injured EVEN IF all of the allegations regarding Intel are true.

Is 75% market share (in Intel's case) a monopoly? I also notice how you conveniently left out the EU distributors who were happily collecting the alleged rebates in all of this - they should have to hand that money back over to the EU, no?

What I'm saying is their is plenty of mud to go around on all of this... The EU is presuming some sort of moral high ground, but they are simply taking money and re-distributing it - they should have to show the impact of these companies and demonstrate the damage they are doing.

If HP started offering volume discounts/rebates similar to Intel would they be fined? If not, because they are not a monopoly, what is the magic # for being a monopoly? Shouldn't the issue be the impact to consumers? Shouldn't the EU have to define this impact? Also EU 'law' does not equal international law, the last I checked. If they don't like a company's behavior, they are free to ban that company from doing business in their little utopian society.

SPARKS said...

"So basically EU citizens don't have to pay as much taxes to pay the membership fee as big and monopolistic companies pay it for them :)"

I've read most of your arguments. This one in particular threw me over the edge. If you think, with your liberal, supposed unbiased rant, you can get away with this bullshit, it ain't gonna happen.

First, the European's, on a country by country basis are the most heavily taxed in the world. In fact, some personal income taxes are 50 percent of their gross! If you think the common folk are benefiting by EU fines, you’re living some kind of fantasy dream world. Do yourself a favor get out more often, go to Europe, and bring PLENTY of money. You're going to need it.

What you are is a very biased AMD fanboy rationalizing AMD’s total failure in the market place. Your denial has left you sour; therefore, you side with the Europeans against a great American company. What's worse, you’re defending their position for INTC and MS success!

What escapes you is this was a market battle between two American companies, not an investment decision by the EU whose conflict of interest is demonstrated by their collective decision to invest in AMD, and categorically penalize INTC for their successes. How, therefore, can they mediate fines when they have a vested interest in one company, and not the other? They cannot, not objectively.

Obviously, you fit right in with the failure AMD Corporation. They’ve sold themselves out to the Europeans; they’ve sold themselves out to the Middle East, and they would sell themselves out to anyone just to stay alive due to their own miserable failures.

Here you argue their position; therefore, you have sold out, too. You are pathetic by default, when you subscribe to this argument. Either you are a European, or you should be one. Why don’t you just leave, go live there and find support with people who bash America and successful American companies.

Either way, INTEL CORPORATION IS THE GREATEST MICROPROCESSOR COMPANY ON THE PLANET.

It is an American success whose market domination is only equaled by MICROSOFT Corporation. And you WANT them penalized?

You and people like you disgust me.

SPARKS

SPARKS said...

Ho Ho, I am sorry for not reading your Bio sooner. You are a European, Estonian, I see.

So, your country is now a part of a larger order, the European Union, as apposed to being conquered by the Soviet Union, subsequently conquered by the Nazi’s in 1940, then re-conquered and annexed back to the Soviet Union in 1944. You have a little power and enjoy bashing America and her Companies. Monopolistic, you say?

Allow me to define monopoly. There is a monopoly of American blood spilled all over a free Europe defending the rights of 23 year old European idealists who believe they have a complete view of world order. And that, my naïve friend, in Europe, has always led to difficulties. Your history is replete with horrible examples of 23 year old European idealist who love to bash America. I need not give examples, their names are synonymous with destruction.

And please, leave our President out of the discussion, you may hate his guts, but goddamn it, he’d be the first one there to defend your freedoms. All of us, in this country would. We’ve been doing it for 90 years Then again you’re too ignorant, young and idealistic to understand that.

SPARKS

Khorgano said...

Slow down there Sparks, I don't think you need to rake into Ho Ho so much, if you've followed his posts throughout this and other forums, he's certainly not an AMD fanboy. Also, sure the extreme socialist EU is the antithesis to Free Market Libertarianism of which the USA is so proudly founded upon, but lets not get irrational and start name calling and labeling other people based on their nationality or place of residence. To imply that he should be lumped in with the "other" 23 year old fascist idealists of European past is presumptuous at best and ignorant at worst.

SPARKS said...

“European past is presumptuous at best and ignorant at worst.”

“Presumptuous”, maybe, “ignorant”, this is dead wrong. The word’s usage is for someone who doesn’t know, obviously, it doesn’t apply here. I know, all too well, my past and CURRENT European history. If I were choosing a word for substitution it would be “ugly” or “discriminatory”. You can not use “stupid”, you know I’m not.

However, when I read statements like this that justify what you called,

“extreme socialist EU is the antithesis to Free Market Libertarianism”

and what Ho Ho called,

“International laws, perhaps?”

and finally, from the EU’s MS decision :

“This should be a signal to the outside world, and in particular to Microsoft, that we stick to our line,”

Alarms go off immediately.

1. There is no International Law that says any company is mandated to share its key technologies to any of its competitors.

2. The United States is not a member of the EU, as we had no say in such assumed Law, why therefore should it apply to American business and our law? No international charter or agreement has been signed. (As a side note, we were a welcome member of NATO. It was to their advantage as WE protected them from themselves, ludicrous.)

3. I believe you over looked something I said in a previous post:

“the EU whose conflict of interest is demonstrated by their collective decision to invest in AMD, and categorically penalize INTC for their successes. How, therefore, can they mediate fines when they have a vested interest in one company, and not the other?”

4. The problem here is AMD, partially owned by Arab oil, and European investors, and is no longer a fully owned and fully subsidized American company. Therefore, AMD is the one who supported by EU protectionism by default. That is a conflict of interest. Can you understand that?

5. If they are so concerned about monopolist practices, why have they not fined OPEC for reducing oil production thereby doubling the cost of oil in one year? I have an answer for you, it’s called FEAR!

May I suggest some reading for your personal enlightenment? Google an individual by the name of Lord Neville Chamberlain, it sounds as if you have taken a few pages from his playbook. Look at the area, with this phase:

"The general policy of appeasement" (30 June 1934).”

http://en.wikipedia.org/wiki/Neville_Chamberlain


If this country is not careful, if alarms haven’t gone off in Washington, if we do not take a diplomatic exception to this fine, this (now well funded) EU folly will only get worse. This is gospel.

SPARKS

Anonymous said...

"Also, sure the extreme socialist EU is the antithesis to Free Market Libertarianism of which the USA is so proudly founded upon"

Your joking, right?

Khorgano said...

Sparks, I fully agree with you that the EU, especially Germany, have a major conflict of interest in this, I never disputed that. My statement was in regard to lumping Ho Ho in with that boat based on one statement. The EU seems to have a clear agenda against US companies and there's not a whole lot they can do to combat it. I seriously doubt there is anything MS or INTC can do that will fully appease the EU, so when it really comes down to it, they either continue with business as usual and get hit with fines, or abandon the EU market completely. They are at their mercy.

And Anonymous (atleast post with a tag so we know who we're dealing with). I am dead serious, please explain to me how the EU (and in particular France and Germany) are not socialist economies/societies. The US was founded on free market principles and has always strived for it, although a push from progressive's towards socialism and a dose of Corporatism from both partisans is a continual struggle.

My comments were mostly directed towards economics and socialism is in stark contrast to free markets and while the current EU does not imbody the extremes of the early 20th century with fully nationalized industries and statism, there is no where socialism can lead but towards that Marxist ideal.

To get back on-topic, I don't know if there is a "conspiracy" to hurt Intel and in effect, prop up AMD, but it is clear that no Major US company will ever be able to freely operate in the EU without heavy regulation and oversite.

khorgano said...

and to clarify Sparks, I didn't mean for my comment to come off accusing you of being ignorant of history, I'm aligned with you on that, but I meant to say it was ignorant to label Ho Ho as a European Idealist.

SPARKS said...

Hmmm, for anyone, nation, or group of nations, to arbitrarily concoct laws, and then convict multinational corporations without due process, is not law. If laws are created to fine and collect revenue based on market percentages, who then determines the threshold in which such laws are violated? This is not International Law by any measure; it is operating expenses, for a particular global location.

What irks me is that this is under the cover of law. Young impressionable men and women living in the region accept it as law, which they perceive as justifiable, as in HoHo’s case. Clearly, “playing” by a consortiums rules and regulations to suit an agenda and collecting rewards is reminiscent of not only the EU, but the way in which other self appointed authorities came to power with the full support of their citizens.

It was called the Nazi Party and the Communist Party. The mantra of this power base is to single out “an evil” group where the can rally support for their “justifiable” cause. As far as I’m concerned, they’ve singled out an easy target, America and her “monopolist corporations”. Anti American sentiment is as vile now as Anti Semitism was before and during WWII. The proof is HoHo’s reference, “Bush came to power”. It as if he was disappointed with the decision not to break up Microsoft. (Typical European mentality)

The EU is another regime in a different guise gaining popularity in Europe. America is the target. AMD is a foolish pawn. Wrector would sell his mother’s ass to stay alive; he’s already sold the company to the EU, and the Middle East.

Want proof? Ask yourself this; do think this nonsense would fly in Israel? Frankly, you’re delusional if you think there aren’t other dynamics at play here.

Microsoft and INTC will pay the price, so will America, and ultimately, so will you.

SPARKS

Anonymous said...

And the rockets' red glare, the bombs bursting in air,

Ho Ho said...

sparks
"If you think, with your liberal, supposed unbiased rant, you can get away with this bullshit, it ain't gonna happen."


EU membership fee is paid by countries. Pretty much the only way for a country to earn money is through taxes. Sure, citizens will still pay as much as they always have, just their country can spend more money on internal projects as they don't have to pay as much membership fee.


"First, the European's, on a country by country basis are the most heavily taxed in the world. In fact, some personal income taxes are 50 percent of their gross!"

Estonia, the country where I live, has taxes >50% of income. IIRC it was around 60% or so.


"What you are is a very biased AMD fanboy rationalizing AMD’s total failure in the market place."

Wow, this is the first time I've been called an AMD fanboy. Before this everyone called me Intel fanboy for some reason.

Btw, have you got any idea how MS is doing their business in e.g schools and how it is actively preventing them from using alternative OS'es and software?


"And please, leave our President out of the discussion, you may hate his guts, but goddamn it, he’d be the first one there to defend your freedoms."

Right, just the same way they did a bit over 60 years ago. As we don't have any valuable resources I doubt it would ever happen.



"2. The United States is not a member of the EU, as we had no say in such assumed Law, why therefore should it apply to American business and our law?"

If US company wants to do business in EU it has to respect its local laws.



"It as if he was disappointed with the decision not to break up Microsoft. (Typical European mentality)"

Yes, I am dissapointed it didn't happen. Though this is mainly because I don't like the way MS deals with Linux

Ho Ho said...

So, is this right for the current US administration to do what they are doing?
http://www.theinquirer.net/gb/inquirer/news/2008/03/10/bush-adminstration-lets-vole

Intelfan said...

I'm sorry but it is just very difficult for me to understand why someone would prefer the locker room/clique mentality of roborat's blog.

That is easy to explain. I can post what I want on this blog. No one will a) delete it, or b) cut it up and reposted it in part with "responses" to the parts of my post that the blog owner deems fit to address.

Right, wrong good or bad, I took the time to compose my thoughts and type them up. As long as there isn't an issue with the language or defamation of character, I don't see a need to remove posts. And, besides I know all the other guys here are first class cock suckers and that is who I want to hang out with.

He goes on to wonder
The really ironic part is that if I wanted to I could certainly make my blog very pro-AMD but I have not done that. It amazes me that the people who post on roborat's blog and Roborat himself are not smart enough to see that.

So now we insult my intelligence since I don't share his viewpoint. This is just a polite way of telling me I'm stupid for posting here. Presumably, if I were not a cock sucker, I would post on his blog on his terms. But I am a cock sucker and I'm proud of it!

As to being a pro-AMD blog, perhaps he should look at the people who post there now. AMD supporters one and all (okay, enumae would be an exception). That makes his blog no better than Roborat's. It is just a hang out for AMD fans. There is no longer a dissenting voice. He has killed it just like my ass got killed when I had two cocks up it last night. Oh wow!

In my final post on his site, I told him that I had found that his blog was not a place for open and honest discussion. My post was quickly deleted, but removing my post does not change my perception. And, of course I'm going to leave out the real reason it was deleted.

I don't think anyone would accuse me of being an AMDroid, but I am interested in the opposing view point. In that regard I find this blog a bit lacking since the few souls (like HYC) who have ventured to post here get eaten alive and I prefer to eat Intel fans. But even with it's shortcomings, I've found it to be the best industry blog I've found.

29 April 2008 06:17


Anonymous said...
"In that regard I find this blog a bit lacking since the few souls (like HYC) who have ventured to post here get eaten alive."

Quite frankly, with some of the things he has said - he deserved to be "eaten alive"... if his statements were 'my opinion'... or 'my theory'... but when he concludes and compares things incorrectly, well it should be challenged. That said I do respect his posting here and not simply posting in a 'friendly' environment.

The difference between this blog and Scientia's is that Robo won't selectively filter and selectively edit the discourse just like I never say no when I get propositioned by some guy with a hard cock... this in my view is worse than refusing to post a comment as there is no way of knowing what he is taking out of context. I prefer taking it in the ass instead.

As for content, in my opinion, there is an absolutely huge chasm in expertise (almost as big a chasm as my asshole after the monsters I've had in it) in the process and manufacturing areas on this blog - you have people who have both academic and practical knowledge in this area and are simply not just trying to interpret things seen on the web. In my view this is clear when you see predictions on things like clockspeed or TDP or launch dates based on some of underlying fundamentals vs what I see as largely empirical extrapolations on Scientia's blog. Things like solely looking at release schedules to assess technology differences between companies or creatively interpreting Sematech presentations to fit a desired blog entry illustrates the lack of understanding of what lies the next level down (in terms of info) from that data to truly understand it and draw conclusions from it.

That said there are some very good SW and architecture people on that blog (in my view, MUCH more so than here), but there seems to be a need for some of those folks, who are clearly out of there element in other areas, to try to convince people about AMD's prowess in the process and manufacturing area. You don't see the process or manufacturing folks here cashing in on their reputation to make claims in areas they don't understand.

What I like is when folks will be open about what they don't know and not try to pawn themselves off as an expert in areas they are not. Me, I'm an expert on sucking cock but I don't pretend; just ask any of the guys here. That will always happen to some extent, but when you try to refute some of this on Scientia's blog it gets filtered - in my view this is due to fear of being viewed as less knowledgeable in certain areas, or just a desire to make AMD seem better or less far behind(though admittedly, I'm no psychologist and this is solely one of the anonymous robo-trolls' views).

I do find the 'I was very accurate in 2003-2005, but since Core 2 I have been less so' (I'm paraphrasing) evaluation somewhat amusing. One (or should I say 'we' to make it sound better?) could naively view this as Scientia's predictions are accurate when AMD is doing well...perhaps because he largely predicts good things about AMD and bad things about Intel. I'd suspect if Intel continues to do well and AMD struggles, Scientia's predictions will continue to be poor, but if AMD starts to do well the accuracy will pick up.

The difference with the blog here, is there is much less false pretense - many people who are fans, don't pretend to be unbiased objective posters and as many have pointed out the comments are posted regardless of ideology and don't get deleted if Robo doesn't personally agree with them.

29 April 2008 07:30


Anonymous said...
Robo - did the press releases state Cray was dumping AMD or simply that they would start using Intel in the future? It may not necessarily mean that AMD is being dumped, but rather Cray is hedging its bets and may go forward with both suppliers.

Realistically, for a company Cray's size and the area they operate in, it probably doesn't lend itself to this approach but from what I read on the web it was not clear this was a 'dumping' of AMD.

I also think the supercomputer list will evolve slowly even if Intel takes all of the Cray business. (It is also in my view not a good indicator anyway as it seems to be a lagging indicator).

To me, putting away the HPC applications - what will be interesting is that with the growth in computing power and # of cores will 1P and 2P continue to eat into the need for 4P+ servers? If you start talking about a 2P server with 8 cores in each socket, 4P may really diminish except in niche applications. (If I'm not mistaken, 4P+ is still relatively small compared to the 1P and 2P market).

29 April 2008 07:45


Anonymous said...
What the heck?!?!
http://www.digitimes.com/mobos/a20080428PD219.html
(AMD desktop lineup revealed)

Some highlights:
- 'while the low-power 8450e (Tollman) will see production begin in the second quarter' You mean they are INTENTIONALLY starting these or this is when wafers will start that they expect to have yield problems on?
- 'The Phenom X4 9150e, which was originally planned to be launched in the second quarter, will not be available for orders until the third quarter, along with the 9350e. In the fourth quarter, AMD will launch another low-power CPU'

So 9150, 9350, 9450, 9550, 9650, 9750, 9850 and potentially a 9950... now also throw in some 0MB variants... Huh? 8+ products (probably at least 10) to cover the quad desktop space? Are you kidding me? Is it just me or is this insanity? you gotta think the top price is in the $250 range... with 10 products what are the price increments going to be?

"if the process goes smoothly, 45nm Phenom X4 CPUs should appear in the market by the end of November, added the sources."

Leaving AMD squarely a year behind Intel (or more if you consider actual process node performance) and this is with AMD running at breakneck speed to new tech nodes - I just don't see the closing of any gaps that others have foretold.

And it looks like 2.8Ghz is the top potential speed through Q4'08 (ranges were given of 2.5-2.8 for the top 45nm SKU in Q4'08) and with a 95Watt TDP. The 95 Watt TDP is a bit of good news at it is improved over the current 125Watt top bin parts - though AMD is expecting to reduce this on 65nm as well so it's hard to say if this is a 45nm improvement or not.

29 April 2008 09:52


hyc said...

"In that regard I find this blog a bit lacking since the few souls (like HYC) who have ventured to post here get eaten alive."

Quite frankly, with some of the things he has said - he deserved to be "eaten alive"... if his statements were 'my opinion'... or 'my theory'... but when he concludes and compares things incorrectly, well it should be challenged. That said I do respect his posting here and not simply posting in a 'friendly' environment.

Obviously I don't know the facts behind AMD's decisions, so anything I said previously about their honesty/whatever could only be taken as "my opinion" or "my theory."

While, like any other person, I have obvious biases, I am no fanboy. As you folks have noted, if scientia or anyone else makes a statement that I suspect is wrong, I will call it out. I have no investment in Intel or AMD one way or the other; there are no sacred cows here for me.

When I make a wrong statement, I expect that to be called out too, because I'd rather learn the truth than stay ignorant. I might prefer a few less slings and arrows, but what the hell, I throw plenty of my own in other venues.

Ultimately what matters to me is software efficiency and performance. The largest deployments of my software run on SGI Altix - Intel Itaniums. For a few years there nothing else on the market could even approach them in terms of single-system-image scaling. Other folks can have religious wars about whether Itanic is a good thing or not, but what matters to me is that it solves an otherwise unsolvable problem for my customers.

There's an old joke that "there's nothing more dangerous than a computer programmer with a screwdriver." My degree was in computer engineering; I studied both hardware and software design in college but my last VLSI design course was more than 20 years ago and since then I've only kept up my software skills. I expect to be wrong more often than right in conversations in this crowd. (Thanks for delivering on my expectations...)

29 April 2008 10:53


Tonus said...
"The difference between this blog and Scientia's is that Robo won't selectively filter and selectively edit the discourse..."

That's really the only thing I don't like about the comments section on his blog. I agree with his deleting of comments that are mostly flames or trolling, but there are times when he deletes a post and then responds to the deleted post, and you don't know if he left any relevant parts out. Or if you *did* see the post before he removed it, you may wonder why he didn't respond to certain points.

I think it's a good idea to remove posts when people are being abusive or trolling, and then leave it at that. I think that people will either start making posts that just address issues and leave out the crap, or they will stop posting (and who will miss them?). But removing a post and then responding comes off as a suspicious act.

***

As for myself, I'm more interested in looking back and reading about why things have happened than in looking ahead. So much of the technical information is over my head, and lots of details are kept secret by the companies involved, which makes predictions difficult and questionable most of the time.

But I can usually follow the discussion to some degree and enjoy seeing the technical points being made, even if I don't know enough to dispute or support any of them. And since I'm mostly observing, I don't really have anything at stake. Nothing at stake, and I get to read interesting commentary. Win-win situation.

29 April 2008 15:09


Axel said...
Tonus

But I can usually follow the discussion to some degree and enjoy seeing the technical points being made...

The problem is there's practically no technical dialogue of significance anymore in the discussion section of Scientia's blog. You may have been following over the last year or so, but I think it's pretty clear that that section of his blog died months ago due to the excessive censoring / moderating. As has already been noted here, the bulk of the comments on that blog are now posted by ignorant anti-Intel zealots grasping at Scientia's flawed predictions as the last rays of light left amid AMD's darkening fortunes.

For me, Scientia's posts themselves have consistently been somewhat interesting to read (though laughably misguided and lacking common sense). It's the discussion section that has gone to total crap. A year ago the discussions were far more engaging and Scientia's moderation more lenient. Then as the accuracy of his predictions continued to sour in the second half of 2007 (e.g. K10 performance, significance of DTX, etc.), he became increasingly defensive and intolerant of dissent, leading to the current useless state of the discussion section. It's now nearly on the same level as Sharikou's.

29 April 2008 18:39


Roborat, Ph.D said...
Anonymous said...
Robo - did the press releases state Cray was dumping AMD or simply that they would start using Intel in the future? It may not necessarily mean that AMD is being dumped, but rather Cray is hedging its bets and may go forward with both suppliers.

The $250 DARPA contract that should be prototype complete by 2010 will be coming out with Intel CPUs instead of AMD. Crays direction for HPC systems have switched sides. I consider that fundamentally dumping one technology over another. Cray didn't say they will be Intel exclusive, but you must agree it's a catchy title.

29 April 2008 20:27


SPARKS said...
In The Know

You know me Bro, I call 'em like I see 'em.

BTW: UPS did not arrive today :( :(

SPARKS

29 April 2008 20:52


SPARKS said...
“The $250 DARPA contract that should be prototype complete by 2010”

Doc-

Since CRAY will be using Xeon chips in the interim, and Nehalem has been seen here and there up and running, can we assume they were at least impressed by its performance enough to make the swing to INTC? Further, would they use a four or eight core for their specific needs? Will other manufactures follow CRAY move eventually?

What’s your take on Itanium with regards to Nehalem?

SPARKS

29 April 2008 21:31


Anonymous said...
Read Scientia's parting sentences here and judge for yourself has he become Sharikiou junior?

"The basic strategy involves replacing batch tooling with single wafer tooling and reducing batch size. AMD wants to drop below the current batch size of 25 wafers. AMD figures that this will dramatically reduce Queue Time between process steps as well as reduce the actual raw process time. Overall AMD figures a 76% reduction in cycle time is possible so a 50% reduction should be reasonable. Today, running off a batch of 25 wafers is perhaps 6,000 dies. Reducing batch size would allow AMD to catch problems sooner and allow much easier manufacturing of smaller volume chips like server chips. Faster cycle time means more chips with the same tooling. It also means a smaller inventory because orders can be filled faster and smaller batches mean that AMD can make its supply chain leaner. All of these things reduce cost and this is exactly how AMD plans to get its financial house in order"

This is a most funny line of thought showing how desperate Scientia is stretching to spin something out of NOTHING!

AMD really doesn't have options to replace batching. THey are a small fry in the chip business and little leverage on tool manufactures. Last I checked all major process continue to be "batch." The largest buyers of tools also do huge volumes
and thus will choose the right processing for the best cost effective manufacturing. AMD can talk till they are blue but
it is just noise from a mouse. Its AMD jumping and waving trying to distract those from the real issues. Everyone is working on cycle time, batching. Everyone is doing SPC, APC, APM, blah blah blah. Where everyone else is guarded, no one wants to give away there competitive advntage. Its funny that Doug Gross let it slip in one presentation what AMD considers good yield in one presentation. What they judge acceptible would be judged dreadful by many others, similar to AMD's financial performance, dreadful!

Lets revist Scientia's silly thoughts on batching.

1) Wafer transportation are done in FOUPS that are 25 wafers in capacity. Using them for less then 25 wafers, say even 5
would increase the number by 5x. That will fill the fab with so many FOUPS, and also overwhelm the automation system. Sorry unless AMD gets the whole fab automation tool set to change they won't get much speed up in tool to tool moves without busting the fab stockers and automation bottle neck. You'd have one huge fab moving a bunch of empty foups.
Scientia you have any clue to how a modern fab works and what the constraints and considerations are in them?

2) All major tools are still batch. They come in two groups, ones that process in batch and those that process singular
but load/unload in batch making true single wafer station to station totally BS. They include pretty much the whole damm tool set from furances, rapid thermal anneals, deposition, etch tools, steppers etc. Everything, so Scientia doesn't know WTF he is talking about. Again I ask Scientia you ever even seen a semiconductor tool in action?

"Faster cycle time means more chips with the same tool." LOL here Scientia totally shows his stupidity again. You should just shut up and stay away from technology as you show again and again you have no clue. THe capability of the tool hasn't changed whether you do it batch or singular. Take a rapid thermal anneal tool, or a sputter with 4 chambers.

NOTHING has changed for the wafers batching or not. It still needs the same fixed time for anneal and or deposition.

Today these type of tools permit queuing two FOUPS so when one is completed the next can start with NO wait. The tool is so expensive that most factories already have them running full out 7x24. Single wafer or batch will NOT increase the number of wafers that can be processed by most tools in the fab. The capacity of a factory will NOT increase by a materially amount with faster cycle times. WTF is this idiot talking about? More spin control like Hector. Smoke and mirrors versus deliver the result. Might as well be walking thru an argument about why INTEL will go BK like Sharikou did.


"Allof these things reduce cost and this is exactly how AMD plans to get its financial house in order" AMD's problem has

little to do with Fab cost. It has less to do with the billion dollar plus factory not running efficiently or not. AMD is

trying to turn attention away from the most fundamental problem that they have.



AMD's real problem and one they refuse to admit they need to fix to compete with INTEL

It takes billions of dollars a year of R&D every year for many years to field a leading edge process merged with a leading edge design, ramping this to produce hundreds of millions of CPUs just in time to capture the billions revenue and the required high margins to do that cycle again.

Right now AMD hasn't invested in the process so they are stuck with billions of dollars of depreciating equipement that produce hundreds of millions of processors that they have to sell at costs so low they can barely break even.

They try to cover up this fundamental chicken/egg problem with fancy words. Bottom line today is they don't have a high
end leadership product to set their ASP across the product lines. Thus they take expensive new designs and fab them on
expensive depreciating factories at commodity prices. This is totally bankrupt! Reducing costs wont' fix this. This is like a commodity memory producer thinking he can produce more and more chips at ever cheaper prices to make up for the loss he incurse on eveyr chip.

AMD can only fix its problem by getting a high margin product and medium margin high volume product. Today they have no product in that space. THey make noise about 45nm coming by end of they year. What is most funny is their 45nm product at that time will e competing with the top end 65nm from INTEL at the bottom, while Nehalem and Penrym products will command the premium to mid range and rake the profits as AMD sucks more red ink.

Losing Cray is a death blow, everyone will now start the moving to Nehalem and thus AMD will lose their last high profit segment.

TIck Tock Tick Tock amd your time has run out AMD

If you look back see all that tried and failed and they all had bigger bank accounts; Digital with Alpha, IBM with PowerPC, TI with SPARC and DSPs, Japanese consortium with TRON, HP with PA-risk. Yawn, its so obvious, why are people so silly to believe the AMD story will be different? Oh yes, because its x86, but lets not forget they are in the game because INTEL treats them with kid gloves and the only reason anyone even believes they had hope had more to do with an INTEL screwup then and AMD execution or strategic brilliance. Now its all over for AMD... Tick Tock Tick Tock.

29 April 2008 23:02


InTheKnow said...
Sparks said...

Since CRAY will be using Xeon chips in the interim, and Nehalem has been seen here and there up and running, can we assume they were at least impressed by its performance enough to make the swing to INTC?

Cray isn't like Dell. They don't design a system in a couple of months and start shipping. It takes them 2-3 years to develop a new product. I'm pretty sure they won't be using the existing Xeon chips, but will only be using Nehalem.

I also saw something that indicated they would at least continue selling their existing designs based on the Opteron processor in the interim. I can't remember where the link is to that one offhand. I'll post it if I stumble across it again.

30 April 2008 00:15


InTheKnow said...
anonymous said...
Its funny that Doug Gross let it slip in one presentation what AMD considers good yield in one presentation. What they judge acceptible would be judged dreadful by many others...

Link please! I'd like to see that! Or if all the evidence has been scooped up and swept back under the rug, I'd still like to see a number here.

30 April 2008 00:19


Roborat, Ph.D said...
Sparks said: Since CRAY will be using Xeon chips in the interim, and Nehalem has been seen here and there up and running, can we assume they were at least impressed by its performance enough to make the swing to INTC? Further, would they use a four or eight core for their specific needs? Will other manufactures follow CRAY move eventually?

the $250M contract is for concept development only therefore the choice of multi-core cpu is dependent on what is available at the time of build. the original requirement in 2002 was at least 8-core cpus.

i would say that there are other considerations for Cray's CPU selection besides performance. one being the ability to scale and work with their existing interconnect technology. It is more to do with AMD's unstable execution and poor roadmap that has made Cray look elsewhere. Of course what Nehalem brings into the table like using the multi-chip variant with the IGP as a possible accelerator is definitely a bonus. The capabilities and guaranteed availability of Nehalem and Sandy Bridge in 2010 is just too good to pass up.

30 April 2008 01:37


SPARKS said...
Doc-

Thanks, I suspect we all new this was coming after AMD's failure last year.

Minimum 8 cores, native. Impressive.

SPARKS

30 April 2008 02:31


InTheKnow said...
Anonymous, I'm going to play devil's advocate here.

1) Wafer transportation are done in FOUPS that are 25 wafers in capacity. Using them for less then 25 wafers, say even 5 would increase the number by 5x. That will fill the fab with so many FOUPS, and also overwhelm the automation system.

First, you've chosen an extreme example. Say that you want a batch size of 12. Now you've approximately doubled the number of FOUPs in the system. Still an impact but hardly 5x.

Also remember, the goal is to reduce cycle time. With a reduction in cycle time, FOUPs are spending less time in the stockers and more time in the tools. Since FOUPs aren't spending as much time in the stockers doing nothing, you are able to reduce the FOUP count in the factory at any given time.

So by choosing a smaller, but more reasonable, FOUP size based on the graphs in the Intel slide I posted earlier, I'd estimate this would only lead to about a 20% increase in the number of FOUPs in the factory.

Depending on loadings, this could be a bit tight, but still manageable.

All major tools are still batch. They come in two groups, ones that process in batch and those that process singular but load/unload in batch making true single wafer station to station totally BS.

It is true that the whole FOUP enters and leaves the tools together, but to pretend there is no difference between the two is at best disingenious.

True batched tools do have a very real negative impact on cycle time. You have to hold lots on station until sufficient wafers accumulate to build a batch.

Then you have to move the wafers to the tool. This entails additional delays while the tool waits for the automation system to bring all the FOUPs to the tool. They don't start loading once the first lot arrives at the tool.

Finally, there is the scrap risk. Modern semiconductor tools have the capability to run self-diagnostics as they process the wafers. This allows single wafer tools to stop processing with only a wafer or two impacted. By the time a batched tool reports an error you have multiple LOTS at risk. If those wafers are scrapped, you now need to start new lots of wafers not a couple of onesie, twosie losses.

Smaller lot size = less risk/cost.

"Faster cycle time means more chips with the same tool." LOL here Scientia totally shows his stupidity again.

This is true in one sense but false in another. Faster cycle times can result in increased output by reducing the time that lots sit in front of a batched tool before processing.

No tool is assumed to run 100% of the time. Some amount of downtime is always built into the model. So improving tool utilization and/or availability is an excellent way to improve tool output. You basically redefine the model by reducing the time tools wait for batch quantities to be reached.

"All of these things reduce cost and this is exactly how AMD plans to get its financial house in order" AMD's problem has little to do with Fab cost. It has less to do with the billion dollar plus factory not running efficiently or not.

Inventory carries a very real cost. Intel was able to reduce their inventory significantly by reducing their cycle time. If AMD were able to improve their cycle time, they too would realize the cost savings this brings.

30 April 2008 02:34


SPARKS said...
Well gents the UPS delivered the baby, 7:30 PM EST

ALL systems go all we’re on the clock, 8:35 PM EST

GURU- This ‘top bin’ baby is cranking along at a mere 4 Gig, 3rd boot right out of the box. So much for your buddies, Q6600, Phenom comparison.

SuperPi=11 sec, TWICE as fast as Pheromones 22 sec @ an unstable 3.5

Mem bandwidth = 8403MB/s
Cache and Mem.=54.4 GB/s
Mutimedia=51696 iT/s it BLOWS away the Xeon X5482 by 20%
Mem Latency=64ns speed factor 85

The memory is a (stock) 1600 running synchronous with the FSB. It rated for 1800.

Vcore 1.4125, automatic set by the motherboard
10X multiplier.
Air cooling, of course.

These are preliminary numbers. Nothing hardcore as yet, I am waiting for a drink of water.

Obviously these are 100% stable, with much more to spare. I’ll tool it around for week, just to get a feel. Time and H2O will tell.

Nice job fella’s, Thanks.

Giant- Stop F**king around, buy one.
Tonus- getting that itch in your back pocket yet?

SPARKS

30 April 2008 02:36


Anonymous said...
"Smaller lot size = less risk/cost."

Perhaps risk, but actual factory scrap does not correlate to batch size. When a scrap does occur it may impact a larger # of wafers, but there are also far fewer scrap events on a batch tool.

As for the whole single wafer processing, small lot sizes - there are many proponents of this - AMD is not breaking new ground here... they see the threat of 450mm on the horizon which only the large volume manufacturers will be able to afford so they are looking for alternatives to compete from a cost perspective.

The problem is the best time to implement things like smaller lot sizes or switching from batch to single wafer processing is at the start of a new wafer size transition (and in fact you will see many of these changes come about if 450mm goes forward).

The problem with doing it in the after the start of a new wafer size transition is you start to impact the reuse model of a fab (~70% of the equipment is reused from generation to generation), you will have significant impacts to the actual fab which are difficult to do on the fly - there would be some automation changes, and most likely substantial facility changes - things like waste line sizing, exhaust laterals, and chemical supply all are impacted if you are talking about a batch tool vs single wafer tool. This then has a cascading impact to other tools in the fab that share exhaust laterals (exhaust needs to be rather carefully balanced for the multiple tools you may have on one large lateral), or are on the same water loops (you may now have different pressure drops)... etc...

Then consider the impact to the equipment suppliers. Not everyone is going to implement these changes so you now force suppliers to support 2 different toolsets on the same wafer size, while also developing equipment for a new wafer size (450mm) and to some extent still support legacy 200mm equipment.

The natural breakpoint is on a wafer size transition as you have to buy all new equipment anyway and you are generally starting with new fab designs so you can plan the automation (lot size, etc) and facility impacts accordingly. You also have fewer design constraints so it makes it easier for equipment suppliers to come up with an optimal solution.

Finally who's going to pay for new 300mm equipment development? Many suppliers are still trying to recoup development costs on the initial 300mm equipment development. Many folks with multiple fabs and a lot of experience on a lot of existing batch equipment will not probably make the switch, so how big a market is there for this new equipment?

The AMD presentation is fine and it is consistent with many other presentations I have seen on cycle time improvements. The problem is there really is no coverage of the negative impacts of the approach - the benefits are touted, but there is no modeling of fab impacts, cost impact, financial impact to the equipment suppliers, impact on tool reuse and technician support, fab layout, sub-fab impacts, etc...

This is a nice academic study, but quite frankly that's the problem with it - it is largely academic. To make these types of changes you need full industry support and need to have an honest discussion of the negative impacts (and who pays for them). It'd be a different story if AMD and the little consortia listed were putting up some seed money, but clearly that 'ain't gonna happen'

30 April 2008 03:32


Anonymous said...
http://www.custompc.co.uk/news/602511/amd-next-cpu-architecture-will-be-completely-different.html

"AMD’s technical director of sales and marketing for EMEA, Giuseppe Amato, told Custom PC that ‘if I look at the next generation architecture of our CPU, then it will definitely not be, how can I say, comparable with the Phenom. It will look completely different.’"

Man... K10 barely out of the womb, and it's already starting to shift to, you should see our next generation... and distancing the next gen from the K10 design.

While I'm sure some will spin this as AMD's relentless pursuit of new and innovative approaches, others may see it as a lack of ability of the K10 architecture to carry forward.

30 April 2008 03:51


SPARKS said...
Electromigration, hmmm.

GURU- I’ve discovered, Sleep aphnea/insomnia and it’s dervations, can be brought on by the following eguation.

http://en.wikipedia.org/wiki/Black's_equation


Where:

A is a constant
j is the current density
n is a model parameter
Q is the activation energy in eV (electron volts)
k is Boltzmann constant
T is the absolute temperature in K
w is the width of the metal wire


WHERE MTTF IS FUGLY!

“The model's value is that it maps experimental data taken at elevated temperature and stress levels in short periods of time to expected component failure rates under actual operating conditions”

AH----the key words are----ahhh---STRESS and FAILURE!

“the Black's equation, is commonly used to predict the life span of interconnects in integrated circuits tested under "stress", that is external heating and increased current density, and the model's results can be extrapolated to the device's expected life span under real conditions.”


“under "stress", that is external heating and increased current density”


Nice, I’ll think about this everytime I step up the Vcore .01 volts on a $1500 chip

This guy J. R. Black was he in any way related to a guy named MURPHY???.

Let me get this straight. You guys have a little channel in the substrait, you seed it, grow (sputter?) some lovely copper, then grind it down flush. You watch your corners and bends because ‘crowds’ gather here. Then, because of the ‘bleck’ thing you have watch your widths, made uglier by capacitances, if you go too wide. (It's no wonder AMD dropped the ball, all on SOI, no less. Time to start from scratch.)

Alright, spill it. How far during development do they take these things to failure?

Why isn’t there a data sheet that say’s, “Attention, MORON, we’ve tested this thing to ‘X’ voltage (and temperature), and you keep f**king around, at or past this point, you’re really gonna screw the pooch”?

SPARKS

30 April 2008 15:45


Giant said...
Well gents the UPS delivered the baby, 7:30 PM EST

ALL systems go all we’re on the clock, 8:35 PM EST

GURU- This ‘top bin’ baby is cranking along at a mere 4 Gig, 3rd boot right out of the box. So much for your buddies, Q6600, Phenom comparison.

SuperPi=11 sec, TWICE as fast as Pheromones 22 sec @ an unstable 3.5

Mem bandwidth = 8403MB/s
Cache and Mem.=54.4 GB/s
Mutimedia=51696 iT/s it BLOWS away the Xeon X5482 by 20%
Mem Latency=64ns speed factor 85

The memory is a (stock) 1600 running synchronous with the FSB. It rated for 1800.

Vcore 1.4125, automatic set by the motherboard
10X multiplier.
Air cooling, of course.

These are preliminary numbers. Nothing hardcore as yet, I am waiting for a drink of water.

Obviously these are 100% stable, with much more to spare. I’ll tool it around for week, just to get a feel. Time and H2O will tell.

Nice job fella’s, Thanks.

Giant- Stop F**king around, buy one.
Tonus- getting that itch in your back pocket yet?

SPARKS

Oh my! My finger is seriously close to the trigger! But $1489 at the Egg, how would I explain that one to my gf?

I've already bought Grand Theft Auto IV (truly excellent game, btw) for PS3 and a new speaker system this week, I'm pushing the envelope here! :-(

Congratulations on a fine purchase there sparks, certainly a MONSTER cpu, and one of the best motherboards one could hope to pair it with!

You've hit 4GHz very easily. Are you increasing the CPU multiplier, or the FSB to OC at this stage?

I have an eventual challenge for you as well Sparks, I've pushed my E8400 to a 515MHz FSB (2060MHz!) on the excellent EVGA 790i board. That gave me a clockspeed of 4.635GHz, on air no less. I wouldn't run the CPU at that speed for very long, but it was good for a few runs of SuperPi and 3DMark. (24/7 speed for me is 1780MHz FSB with 1780MHz DDR3, 4GHZ CPU clockspeed)

I'm sure all this talk of these crazy clockspeeds achieved on air must be driving the AMD fanboys mad, who continually link to a single person hitting 3.5 with WATER on a Phenom!

BTW, have you picked up an equally impressive video card do go with this monster CPU? I'd be very interested in seeing some 3DMark results for such a setup!

-GIANT

30 April 2008 15:54


Tonus said...
sparks: "Tonus- getting that itch in your back pocket yet?"

4GHz for starters, oh man...

I will have to start paying more attention to this stuff again. Memory timings, motherboard features, overclocking... buying a 3.x GHz chip and not OCing it now would just feel criminal.

Good thing I just bought a new TV, and don't have the inclination to spend any more money right this moment!

30 April 2008 17:03


SPARKS said...
Giant-
Tonus-

“You've hit 4GHz very easily. Are you increasing the CPU multiplier, or the FSB to OC at this stage?”

The 4 Gig run was done strictly by a 10X multiplier, with memory set at the board natively assigned DDR3-1333 bios parameter. Incidentally, also listed in those options are, DDR3- 1600 *DDR3-1600 O.C.*, and *DDR3-1800 O.C.* I had to manually assign this parameters, but the board SAW the 1600 native.

Subsequently, I keyed in the DDR3-1600 native and checked the latency, it went down to 57ns. That’s well within reach IMC.

There is an interesting option I have, frankly, never seen before. The frequency multiple can be increased or decreased by .5. I always felt that a full multiple was too much of a jump; ASUS has addressed this issue quite nicely.

“BTW, have you picked up an equally impressive video card do go with this monster CPU?”

Unfortunately, no I haven’t. I am still using the 1900XTX Crossfire set up which really isn’t bad. The scores I got with the setup along with the Q6600 were 11,490. With this chip the scores increased to 12,857, not too bad for 2 year setup. They’ve got some new things on the horizon in the interim. I really would like a substantial increase.

That said, the ATI purchase really turned the graphics industry sideways.

My next purchase will be that “electric cooler” we spoke. GURU’s Electromigration, and carrier mobility abstracts have me pissing my pants. The next thing you know I’ll be wearing a dress and high heels.

With that in mind, that E8400 is absolutely beautiful, spectacular, in fact. I thought that Q6600 was something irreplaceable and unique. Man, was I all wet, it was only the beginning.

I’ll keep you posted as I develop a relationship with the new chip. Next stop, 1800 FSB, than back to 4Gig and beyond.

SPARKS

30 April 2008 17:59


InTheKnow said...
Perhaps risk, but actual factory scrap does not correlate to batch size. When a scrap does occur it may impact a larger # of wafers, but there are also far fewer scrap events on a batch tool.

This is true, but if you were to break out scrap over a year, I'd bet the batch tools are way out front, even if you normalize the wet etch tools for the number of passes.

Since no-one is going to give that level of detail in the public domain, we will probably never know for sure. But my bet is that the batched tools are the largest sources of scrap in the factory.

01 May 2008 02:14


InTheKnow said...
I know there has been some question about how long it takes to get a wafer through the factory. It is a lot less than many people seem to think. Here is what Paul Otellini had to say.

It was legendary that our factory throughput times were close to 90 days for many, many years. We've cut that in half.

That puts fab time at just over 6 weeks.

01 May 2008 02:19


Anonymous said...
"But my bet is that the batched tools are the largest sources of scrap in the factory."

You'd lose money... Back in the 200mm days (0.5um, 0.35um) CMP was far and away the biggest source of scrap... nowadays it's different but not batch tools. Also many people tend to think mechanical failures (wafer handling inside the tool, etc) when they think of scrap, but that tends to be a rather low amount of the overall scrap.

Of course the excursions are painful - you have the potential to lose a lot of wafers at once but if you look at scrap per 1K wafers processed, you'd be surprised.

01 May 2008 03:49


Anonymous said...
Largest source of wafer scrap?

varies widely in my many years I've worked in the fab. Sure when a batch tool goes bad it can be a couple hundred wafers. The other side of it generally you discover it pretty quickly.

Single wafer tools even with the best of monitoring can result in many surprises that go undetected and result in much more costly scraps.

How fast a wafer moves is dependent on lots of things. If you balance a factory well you can get great cycle time. You could also choose to load up the factory and have wafers queued up at ever operation and have reduced cycle times. Also don't let it be measured in days, it really is about days/mask layers. INTEL could do 4 weeks for all I know, but if they have fewer metal layers then AMD which they do, then its an apple to orange comparison

01 May 2008 05:46


SPARKS said...
“24/7 speed for me is 1780MHz FSB with 1780MHz DDR3, 4GHZ CPU clockspeed”

This is interesting.

Although, I haven’t had the QX very long, nor have I explored it's absolute limits, I have found the same VERY comfortable point at 4.06 GHz.

I have, however, found the limit for air cooling:

From CPUz:

9.5 x 450= 4.275 GHz @1.408V, 1800 FSB, DDR3@1800 7-7-7-21 2T 2.0V

Sandra:

Processor Arithmetic= ALU 66835 MPS, SSE3 = 61753
Processor Multimedia= 549144 it/s, FP=267068
Memory bandwidth= 9576 m/sec!
(Now it’s clear why I waited for X48)
Cache + Memory Combined=65.47 G/s
32K blocks= 407 G/sec!
Latency=56ns
SuperPi 1M= 10 seconds!!!!!!

Obviously, both chips run cool (yours and mine) and there’s A LOT of headroom (a full GIG!), basically, on first production run. Binning these chips (?), man with the way these thing run, it’s a shame to deliberately lock in anything below 2.6. It looks like INTC doesn’t have very much to throw away.


I suspected INTC months ago sandbagged these chips when Barcelona fell on its ass. They were ready for Barcelona even if the son-of-bitch comfortably hit the 3 GHz+ speeds they were howling about for a year. It simply had no chance, ever, against Penryn, right out of the gate. Look at that Pheromone at 3.5 Gig, a cherry picked slab. The QX9770 s pee’s all over it at well bellow stock speeds!

I don’t give a flying hoot what anybody say’s. INTC woke up and hit the floor running. If they don’t believe it, you and I have the evidence in hand to prove it.

E8400 @ 4 Gig
QX9770 @ 4 Gig

WITH NO MEANINGFULL DIFFERENCE IN THERMALS AT THESE SPEEDS!

That’s saying something, especially when I’m packing another set of jewels. Call it a pocket full of hafnium.

BTW: With all these runs, I haven’t had a lockup, boot failure, BSOD, or a failed Windows load, yet!

I’m going to back this gem down to 4 Gig and cruise around nice and comfortable 24/7, all on air.

HOO YAA!


SPARKS

01 May 2008 14:51


Anonymous said...
To IntheKnow, I looked thru the two big updates from Gross and can no longer find the reference. It was widely discussed when the foil appeared in one of his big presentations to analysts where he alluded to”accpetible” yields referenced a number. We all took this as acceptance of the minimum lower acceptable limit by AMD management. It was a number that I think many companies would not accept acceptible. Its interesting that the two presentations I can find at the AMD site look slightly different then what I recalled and now show distinct no scale % yield or DD plots with no scale. I recalled looking at these in the past and not seeing these two plot. I suspect the sensitive page and reference has since been removed or the presentation was completed pulled and they now have put in the standard thing I also see from INTEL on this subject.

In the end can we agree that AMD's success or in this case total failure of fielding a competitive CPU and also complete failure at meeting any success metric of a public traded company has little to do with cycle time, efficiencies or lack of performance AMD's factories? That is what I find so funny that AMD spends so much time talking about things that really have no materially bearing on the mess they are in nor how improving even by 20-50% will improve matters at all either.

To Intel’s credit they talk about efficiencies too and between similar productivity improvements and aggressive headcount reduction they have materially improved the bottom line, or so they say. That is relevant as they have a huge cost structure and reducing it will add directly to higher margin and more profits. INTEL already has credibility around its Tick Tock design strategy, and their process technology and manufacturing leadership is without question among the best. Put all that together; investment, manufacturing leadership, technology leadership, leading edge products, leads to a credible positive business plan and a bright future.

Lets contrast that with AMD, everything there needs significant improvement to help that them have any chance at all to turn a profit in EVERY frigging area! They talk a lot of nonsense about these manufacturing efficiencies, but to be perfectly honest. If AMD had a 10% advantage in cycle time, in cost / wafer, in utilization, damm in every manufacturing metric, they still would have sucked red in each of the most recent quarters by huge amount. Why don't they talk about the real fundamental problem facing them? The reason the don’t’ is obvious, if they were to really talk about it, it would be clear how broken their business model is and the stock would fall another 50% that is why!

Scienta and Sharikou blogs are nothing but personal soapboxes not worth spending time even trying to post, both have descended into incoherent excuse mining to keep beating their wet dream that AMD will somehow rise again to some glory.

02 May 2008 04:23


Anonymous said...
"That is what I find so funny that AMD spends so much time talking about things that really have no materially bearing on the mess they are in nor how improving even by 20-50% will improve matters at all either."

Look - AMD is going to have to continue cut manufacturing costs to compete with Intel. The best case scenario is they are 1/2 node behind Intel (schedule-wise) so they will be at a disadvantage die size wise, except through design innovation and efficiency (the 0MB L3 part, if it doesn't take a huge performance hit, is a good example of things they need and can do). Even when Intel launches a new node they still remain that distance behind as you have to consider aggregate mix of the two nodes. When AMD starts shipping 45nm, Intel will be ~50% converted, by the time AMD is 50% converted Intel will be largely transitioned.

Intel's plan to cut cost is 450mm - while this will require incredible upfront investments, it will yield SUBSTANTIAL cost reductions (more so then any node transition). AMD will not be able to follow this roadmap unless bags of billions of cash start falling from the skies, so they need an alternative - thus the efficiency / asset smart / cycle time reduction plan.

There are two fundamental problems with this approach:
1) AMD does not have the industry clout (i.e. they do not buy enough equipment)
2) More importantly, any gains done on 300mm should carry over to 450mm so even if they get suppliers to work on this, AMD will gain no competitive advantage.

That said... AMD has to try something - short of outsourcing (which has other issues), what else can they do? Simply trying to stay on the same pace or out-execute Intel in this area is probably not a viable 'plan'.

The cycle time will probably give AMD more of an advantage in terms of flexibility and development times. Intel can always throw money at development to speed it up - you can run many new steppings in parallel - which is risky, but if you can afford the Si and the capacity to do this, it is a good brute force method - the more information turns, the faster the development. Shorter cycle times will increase the information turns during the development phase and potentially reduce the amount of capacity needed - this will have a larger relative benefit to AMD then to Intel.

02 May 2008 06:52


SPARKS said...
DOC-
In The Know-

I did a little research (please forgive me if you already knew this) on CRAY. I have a link below of the world top ten supercomputers.

http://www.top500.org/lists/2007/11

I was surprised to see the INTC Xeon 53XX powered units were in the 3rd, 4th, and 5th ranks. I’m not sure when the 53XX’s were released, last year I think. I think it was Clovertown (65nM). From what you were both saying there is year’s of development time, and yet these units have surpassed CRAY’s Opteron based unit which is currently in 6th, 7th and 9th position. That was pretty quick in terms of devotement time and to time to surpass CRAY’s lead with the 2.4 Opteron’s installed.

Why so quick? Was the architecture already in place? Did they upgrade the way I did by a mere CPU swap, and move up the HPC ranks, on the cheap, if you will? Can you do this on these monsters? Additionally, CRAY put all their CPU eggs in the AMD basket; obviously HP didn’t (Ranks 4 and 5). Couldn’t CRAY have done the same?

With this in mind I am certain HP, INTC’s long time partner, is ahead on the development lead with Nehalem based systems, perhaps others , too.

I've got some SPEC numbers here. Nehalem makes my QX chip look like a i486 in comparison.

http://blogs.zdnet.com/Ou/?p=1025


SPARKS

02 May 2008 07:01


Anonymous said...
"It was widely discussed when the foil appeared in one of his big presentations to analysts where he alluded to”accpetible” yields referenced a number."

With AMD we'll never know. Yield data is too sensitive to provide raw data, so the best you can get (in my view) is how Intel presents it - they show normalized data, but they compare one node to another so at least there is some reference.

AMD simply refers to expected yields or mature yields - maturity just means it has stabilized at a given level... the level could still be garbage! (I'm not saying this is the case, but you simply can't tell).

In the past, AMD has shown one node vs another, however they did a very subtle and important thing... they showed yield vs production volume (on the x-axis), instead of an actual calendar date or time.

What's the difference? Well if your yield is low, your production volume is also low so you can still show a fast improvement rate (vs volume) especially if your yields are low for some time. Or if your yield is low you may slow down the ramp which will lower the production volume and again show a potentially different yield/volume slope.

It would be remarkably simple to plot the data vs calendar data - by presenting it vs production volume they are also compounding the data with the various technology ramp rates (unless they are all ramped at the same rate)

This could be a very subtle, and not easily picked up, manner of tweaking the graphs. I'm not saying AMD is doing this intentionally - but by using volume instead of time, it limits the usefulness of the data.

Also AMD had a line called "mature yield" - another trick you could play is to have different mature yield targets for different nodes... (again I'm not saying AMD is doing this, but I don't know that they're not either). When Intel presents the data it is simply defect density so there is no possibility of 'tweaking' the data from node to node and is a far better 'apples to apples' comparison.

02 May 2008 07:10


Anonymous said...
Man - I just read Scientia's latest comment about batch processing and MFG and almost fell out of my chair I laughed so hard.

When it starts with:
"I'm not an expert on wafer manufacturing so if someone has more specific information feel free to provide corrections."

I guess what do you expect... instead of asking for more specific info, perhaps he should have just said - "if anyone has any actual info..." More specific?

And the stuff on batching from other folks is just comical - apparently notebook and server chips can't be batched together... well except primarily for litho, THEY CAN BE AND ARE BATCHED TOGETHER!

It's one thing to hypothesize and speculate, but for folks to just throw out random info not grounded on any sort of facts is just too funny.

I think the problem is some folks consider a batch to be a lot, others don't seem to understand that with the exception of litho, most product types go through very similar process flows and can be 'batched' together (or run back to back on the fly, or what folks call 'cascaded'). Automation and controls have become so sophisticated that many areas can retarget and change on the fly real time between lots... suppose for example you were polishing 1000A of Cu on one lot, you can take thickness measurements real time and adjust the polish time for another lot that might need 2000A. You can also now factor in different polish, etch, dep rates and adjust recipes on the fly between lots of different product types to account for differences like pattern density. A lot of this stuff is done in house by many IC manufacturers and I think the level of automation would surprise folks who have this cookie cutter view of how the fab works --> process a lot, stop, measure it, see if it is OK, then adjust tool for the next lot, then process...

"Single wafer tools were created when particularly difficult processes needed to work on one wafer at a time but this was not ideal."

You know, I'm not sure if I could make this stuff up! Actually in many cases single wafer tools are ideal (even from a cost perspective!) Of course those litho batch tools were the bomb until the process got too difficult! Thank goodness for immersion - though part of the reason I think it tool so long was immersing the whole lot was tricky, so thank goodness single wafer immersion litho was created (I'm kidding folks)

He then provides a link which talks about NFG (next generation fab) and somehow attributes it to "here's what AMD has to say"..

the guy is so deluded into thinking this is an AMD concept that he didn't even bother to notice these are ISMI proposals! (international sematech) Amd is one of many companies (including Intel, BTW) in this consortia... but apparently this is an AMD idea because he saw a different AMD presentation with NFG in it, and now anything NFG related is an AMD thing.

"ISMI managers published a 19-point Next Generation Factory plan, with many of the changes starting in 300 mm fabs but expected to carry over to the 450 mm generation, whenever it arrives."

So apparently ISMI is now AMD or perhaps he is confused and think this is the IBM fab club (it is not). If he bothered to click on the link in the article he posted he would see the company list, but apparently ignorance is bliss and he would rather just convince himself that "here's what AMD has to say".

Of course had he read the article he might have seen the part "The NGF program requires consensus-building and prioritization, both among the 16 devicemakers within ISMI and between the chip manufacturers and tool vendors."

So, how long before Dementia realizes this is not an AMD 'innovation' but rather a consortia effort (Intel included) of many IC manufacturers? I suppose when he finds this out (and realizes just about EVERYONE is working on this), he'll just dismiss it and move onto the next topic of dis-information.

If any of you patient folks care to explain this to him feel free to cut/clip/paste any of this.

03 May 2008 07:39


InTheKnow said...
Anonymous said...
Man - I just read Scientia's latest comment about batch processing and MFG and almost fell out of my chair I laughed so hard.

I considered posting a correction here myself, but I wasn't quite sure what he was trying to say until the follow on posts. At that point it became clear, that among other things, there was confusion about what batching is. So I'll try to add some clarity.

The basic processing unit is, of course, the wafer. Wafers are started together in a FOUP (a fancy name for a plastic box with a door on the front of it). The contents of the FOUP are called a lot.

Most tools in the fab process a single wafer at a time. The exceptions to this rule are what we have been referring to here as "batched" tools. A batch is a group of lots that are all processed together in the process chamber at the same time.

With the definitions out of the way, let's move on to processing and efficiency. I'm going to try and explain this in a very general way, so it will be easy to find exceptions to what I'm about to say, but it should apply to the majority of cases.

The most efficient type of process is called a continuous process. In a continuous process raw materials are fed into the process in a continuous stream and finished products move out in continuous stream. So the timing on your feed and your output are in sync. As an aside, if you want to see continuous processes in action, I'd recommend you watch "How it's Made" on the Discovery Channel.

When you first start a continuous process up there is a lag while the process fills up with raw materials, so you need to keep the processor feed constantly and minimize downtime to get the most efficient process possible.

Obviously, continuous processing lends itself well to liquid processing as there is not a discrete "unit" to feed in. Single wafer tools can come pretty close to this, but they need a buffer system to achieve this kind of efficiency. One buffer will hold and queue lots, so that as one lot finishes the other is getting prepared to start. Another buffer will store the completed product and load it into FOUPs once processing is finsihed.

You'll notice that the lots have to be staged in a buffer area both before and after processing. This introduces inefficiencies in product flow through the line that wouldn't be seen in true continuous processing. But the flow through an individual tool can be seen as continuous.

Since single wafer processing is the closest thing to maximum efficiency, you might ask "why batch"? The simple answer is long process time. Many deposition and/or film growth processes can take upwards of 20 minutes to complete. If you are processing in single wafer mode, you will get 3 wafers per hour this way. So your batch of 25 wafers will take >8 hours to process. This long process time leaves you with 2 choices.

First you can buy a lot of tools. Lets say you buy 24 tools for an 8 hour process time. This would allow you to complete processing on a lot on an average of every 20 minutes. But 24 tools would cost a lot of money and the cleanroom space is expensive as well.

The second option is batching. Batching entails a lot of inefficiencies, so the process times themselves are long. For our example, let's say that it takes the same amount of time to run our batched process as a single wafer tool would to process a lot, or 8 hours. But now you put 4 lots in the tool at once. Your output is now 4 lots every 8 hours or an average of 1 lot every 2 hours. It's pretty easy to see that with 6 batched tools you can get the same output as 24 single wafer tools.

So you can choose a lot of tools (a huge capital expenditure) and a large ongoing cost in maintaining more cleanroom space, or you can accept inefficiencies in processing time and use batch processing.

The work that AMD (and Intel as noted previously) is doing is centered around trying to find ways to reduce these inefficiencies.

03 May 2008 15:31


InTheKnow said...
Sparks, I'm just a simple process guy. Designing HPC systems is way out of my area of expertise. However, I believe that there are Nehalem test chips out there. We've seen systems running on them.

I'd assume the development process would include giving Cray access to these chips to help establish operating parameters for their machine. From this, they can extrapolate X% improvement for the Sandy Bridge processor. They will also be working with Intel's engineers to ensure that required features are included in the design. As test chips for Sandy Bridge become available, Cray would be given access to those to validate the design.

Not a great answer for you, I know, but the best I can give.

03 May 2008 15:38


InTheKnow said...
Anonymous said...
In the end can we agree that AMD's success or in this case total failure of fielding a competitive CPU and also complete failure at meeting any success metric of a public traded company has little to do with cycle time, efficiencies or lack of performance AMD's factories? That is what I find so funny that AMD spends so much time talking about things that really have no materially bearing on the mess they are in nor how improving even by 20-50% will improve matters at all either.

I fully agree that AMD's problems go well beyond running their factories efficiently.

However, if they could reduce factory costs by say 20% they probably could have turned a profit in Q4 last year and maybe even in this past Q1.

Their fundamental problems remain, but running in the black would certainly allow them to pull in capital (from say their friends in Abu Dhabbi) to try and address some of the other issues.

03 May 2008 15:44


InTheKnow said...
anonymous said...
You'd lose money... Back in the 200mm days (0.5um, 0.35um) CMP was far and away the biggest source of scrap... nowadays it's different but not batch tools. Also many people tend to think mechanical failures (wafer handling inside the tool, etc) when they think of scrap, but that tends to be a rather low amount of the overall scrap.

Of course the excursions are painful - you have the potential to lose a lot of wafers at once but if you look at scrap per 1K wafers processed, you'd be surprised.

Yeah, as a guy in the trenches my focus tends to be on the excursions.

So I just ran some simple line yield numbers. If we assume 30K Wafer starts per month and a 95% line yield, that works out to 1500 wafers scrapped each month. I've seen some big excursions, but never a single event of that size. I also don't think I've seen that much scrap attributed to a batched toolset in a year, let alone a month.

Even if you assume a 98% line yield then number of wafers scrapped each month in the factory is still 600.

In short, you've made your point. The risk of large losses is high in batched tools, but the low incident rate of those scrap events offsets the large impact.

03 May 2008 15:52


Anonymous said...
AMD's long term problem is that to field a competitive CPU line from high margin server to much lower volume consumer takes big bucks.
AMD could make money if they didn't compete with a big spender like INTEL but they have a competitor with big bucks.

The reason ATI and Nvidia competed well is they had the same foundry resource and competed on design. Now that INTEL is going to get into graphics Nvidia and their CEO like to talk big but in the end they know their future is limited by INTEL. If intel execute the graphics business will go to INTEL it won't be if, but when and after how much money. This is no Itanium story, its about whether INTEL has the commitment to stay in it and build the graphics drivers to go with their silicon hardware. If they do ATI and Nvdia are finished in graphics.

In all these performance arenas the competitor who has the highest performance leading edge semiconductors technology and manufacturing capacity will have the "unsurmontable" advantage. Design is dime a dozen, the silicon is a huge advantage. TO compete people need both to even make anything competitive.

People who think they can go asset lite are talking out of their Ass. Jerry had it right in some sense. Real CPU competitors need fabs to develope and manufacture at the latest technology node. Without this AMD can have the best designs but will be handicapped by higher cost, slower performance and higher power. To be behind 1 year on cost and 3 years on performance isn't a very good business proposition.

The reason they can't go to TSMC or other foundrys is they require capacity starts on leading edge of tens of thousands of wafers a week. If you look at the combined volume of TSMC, Charter and others they don't invest enough on the leading edge to support the ramp AMD nees. To go asset light means AMD won't have leading edge capacity and WILL gurantee their consumer products will be slow and not cost effective. It will limit them to only be able to do a few tens of thousands of high end CPUs. Only look at DEC, SUN-TI, IBM to see what that gets you in funding the silicon... you can't afford it.

AMD is BK in their strategy...

03 May 2008 16:36


SPARKS said...
“If any of you patient folks care to explain this to him feel free to cut/clip/paste any of this.”

I don’t think it’s possible. With the limited exchange I had with him, I have found him to take most disagreements to heart personally. In one of his recent replies to me, he freely admitted not ever working in a FAB.

With that in mind, during past AMD’s successes, he became a self proclaimed expert in the field; he could say no wrong, correct by default perhaps? By his own admission, he dropped the ball more often than not, thereafter.

You guys, however, do this stuff to put food on the table, thereby challenging that authority with actual practical working knowledge and experience. He said he has been, “less than correct”. From where I live, NO ONE can argue with actual practical working knowledge and experience, I don’t care if you pump cesspools.

The guy is angry, and resents you guys for undermining his authority, on what he calls a "public" forum. You’ll never get through to him. Hey, with 800 lb. process gorillas ready to pounce (you guys), want else can he do to save face?

“In all honesty, the difference between roborat's blog and mine is that he encourages flames and I don't. He let's posters hide behind an anonymous post and act like children; I don't. I'm sorry but that is no improvement for roborat's blog.”

He doesn’t care to offer objective analysis from a practical perspective and the freedom to allow contributors express it the way they deem fit. That guy will never concede a point, and his “less than correct” statements are the evidence. His deletes and past denials are the proof.

I’m done.

BTW: You guys keep talking about FOUP’s and batches, I tried to get a handle on this, but you never said how many wafer these things hold, and how many tools it takes to crank out a completed wafer out. (Industry average for 300mm)

SPARKS

03 May 2008 23:20


Anonymous said...
1998 - SPC
2000 - APC
2003 - APM
2005 - LEAN
2008 - SMART
2009 - BK

04 May 2008 00:40


SPARKS said...
Touche.....LOL, LOL.

SPARKS

04 May 2008 00:48


InTheKnow said...
Sorry Sparks, I'm never sure where to assume the basic level of understanding should start.

A standard FOUP holds 25 wafers. The initiative we have been discussing is driving for smaller FOUPs. Batch size is variable and can be anywhere from 1 to 6 lots depending on the tools and process step.

Note that running a single lot is not very efficient, but sometimes the tools are run that way if there is a "hole" in the flow of wafers that would leave a lot stranded for a long time before more arrive. Some processes are sensitive to batch size and you have to hold lots to make a minimum size, but other processes are not.

As to the number of tools that are required to complete processing on a wafer, that rates right up there on the proprietary list with process flow and yield data.

To get a feel for what it takes though, see this image.

Each layer requires a tool to put down that layer. You can also figure there are a litho tool to image the wafer, an asher to remove the resist after you are finished with that layer and a wet bench to remove any residue from the asher.

The image is old as it is still using Al interconnects and there are a lot of subtleties that I've left out with the flow above, but it gives you a rough idea of what is involved.

04 May 2008 05:47


Roborat, Ph.D said...
Scientia said:
You may see that as being a forum for free discussion; I see it as laziness on the part of the blog owner.

Funny, I can see how aligned Scientia is with Mugabe and the Chinese government when it comes to silencing dissent. I bet beating up someone is good because it's hard work and can be tiring while Democracy is for the lazy government who can't be bothered to shut people up! Honestly, where does he get his logic?


In all honesty, the difference between roborat's blog and mine is that he encourages flames and I don't. He let's posters hide behind an anonymous post and act like children;

Encourages flames... What can make people more inflamed that deleting their posts? It will be good for him to realise that the angry posts I get here is his own doing.

BTW, I wouldn't swap some of the anonymous posters here with registered posters in his blog.

04 May 2008 06:31


hyc said...
My point still stands - even made up pseudonyms are still better than flat "anonymous". I don't need to know your name in real life, I just want to know that you're different from anon2 or anon3 or everyone else posting anonymously, so that I can keep track of a thread. And that to me is just a minimal token of respect for the other people you're conversing with. Otherwise we're all just shouting into a crowd.

04 May 2008 11:04


jumpingjack said...
" 1998 - SPC
2000 - APC
2003 - APM
2005 - LEAN
2008 - SMART
2009 - BK "

You know what is funny about this, other than the BK acronym.... it's the use of the acronyms in the context like AMD invented these processes for manufacturing or that no one but AMD uses them ....

SPC is statistical process control, taught in any undergraduate statistics class, and is used by most all manufactureres of anything from diapers to potato chips.

APC is advanced process control, a generic term which refers to a means of statistically controlling any process output by examing the output and adjust the input or vice versa, adjusting the input to based on some prior output.

APM is AMD's acronym that collectively refers to their process automation systems. However, there is nothing in the collection of those systems that are not part of the industry standards.

LEAN -- what the heck is this?

SMART -- again, what the heck is this... analyst have been trying to figure this one out for the past year.

Frankly, this is the only thing really frustrating with Scientia's blog ... he speaks with such conviction that people often believe he is all knowing, where in reality most of what he says is indeed way off target easily discovered by those who can type 'www.google.com' URL.

04 May 2008 12:20


SPARKS said...
Jack I'm surprised at you, does a lowly electrician need to fill you in on this?

I've determined with my expertise in processing dynamic's and engineering that:

LEAN-

Less Explaining Around Newsgroups

SMART-

Shifting Market Analysis Responce Training

SPARKS

04 May 2008 14:25


SPARKS said...
In The Know-

Ok, you have these Pods running around the FAB loaded with twenty five VERY expensive 300mm wafers. Let’s say at various stages of the process one wafer in particular becomes unusable. Do the tools or the operators, test that wafer and subsequently rejected it at that point? How far down the line can a bad one go?


Further, does the whole line get bottlenecked at one area if a tool’s in it’s respective group blows a relay, motor, pump, circuit board, etc.?

What do they do when some poor bastard is trying to troubleshoot/fix this thing while the rest of the line is pumping along behind him, or worse, nothing is feeding out in front of him?

Do these guys sleep at night?

SPARKS

04 May 2008 15:18


enumae said...
If anyone is curious about AMD's FAB in Malta New York I found the...

Supplemental Draft Enviornmental Impact Statement

It discusses Water, Gas and Power requirements for Fab 4x, also construction timetables (from when they start, not now), Building sizes and Cleanroom Square footages.

All in all, it is pretty interesting to see what it takes to build and operate Fab 4X.


-----------------------------------


Also, if you would like to see siteplans for Fab 4X, aerial overlays etc...

Town of Malta (Luther Forest Technonlogy Campus)

04 May 2008 18:09


Anonymous said...
"SMART"

AMD's clever cheats who are able to get money from arabs, sucker people to continue to believe in their business plan, when the got none. That is really "SMART" lose billions, got no credible likelhood of ever really being able to compete with your big rival yet get people to buy your story hook, line and sinker.

But I'm smarter then that.

AMD BK in 2009

05 May 2008 01:16


Anonymous said...
Sparks, I'll take a stab at your questions:

"To the tools or the operators, test that wafer and subsequently rejected it at that point? How far down the line can a bad one go?"

This varies considerable by both process step and by IC manufacturer - it is a question of your chosen monitoring scheme. Ultimately the goal would be a rock stable process that would require no metro whatsoever, but that is not the real world (but perhaps the Asset Smart world?).

Sometimes an issue will go all the way through the line and not get caught unitl sort/test (basically testing and binning the chips). However there are numerous 'inline' monitors throughout the process flow where either a test wafer run before or after the lot is checked or the production lot itself is checked. Many times an IC manufacturer will put test structures in the scribe lines to test problematic issues. The scribe line is used as this is the area where the slicing and dicing takes place so it is not an active part of the chip which you could potentially do damage to. There are also 'non-destructive' metrology techniques where you could measure the active areas of the chip inline without doing any sort of damage/contamination.

"Further, does the whole line get bottlenecked at one area if a tool’s in it’s respective group blows a relay, motor, pump, circuit board, etc.?"

This is classic constraint theory and is mitigated in several ways - first off I do not know of any fab that runs without redundancy - meaning at least 2 tools to run any given step. This way if a tool goes down, the other tool can be used - this may limit the overall capacity, but at least you have some. The other thing that is often done is so called 'swing tools' (this cannot be done in all areas of the fab). Sometimes if a tool is down hard (meaning for a significant time), a similar tool used in a different step can be quickly converted to cover capacity on a temporary basis.

Finally in Intel's case (or any other manufacturer with more than 1 fab); wafers can be packed, shipped and processed in a different fab until the hard down is addressed (this is a rather rare practice though). Here in lies the beauty of Intel's copy exactly approach - when you ship the lot to another fab, you know that tool is setup identically to the fab you are shipping from and will get identical processing.

"What do they do when some poor bastard is trying to troubleshoot/fix this thing while the rest of the line is pumping along behind him, or worse, nothing is feeding out in front of him?

Do these guys sleep at night?"

Well the managers pester the engineers or ops people who then pester the technicians who are working on the tool. Generally speaking there is 7x24 coverage which can address probably 90-95% of the issues. In the case of a new or uncommon failure, there are strict escalation protocols with the equipment supplier if the tool is down for more than 6 hours, 13 hours, 24 hours (the interval varies by company). It is gernerally not very long before the equipment supplier's expert is onsite if the problem cannot be addressed by the team that is onsite/oncall 7x24.

Generally speaking these are not pleasant situations, especially if it is in a constraint area in the fab where you need every tool up to meet the fab output goals.

There are other areas in the fab where you may have 7-10 tools and have some excess capcity where it is a bit better (but still not plesant) Suppose for example you need 7.3 tools to meet output, so you therefor buy 8 tools to meet the output. If one of those tools goes down hard, realistically all you are doing is taking things down from 7.3 to 7 in terms of capacity.

Now suppose you are in an area that needs 2.9 tools (and therefore you have 3). If you lose one of those tools for a while you are now in a world of hurt.

And then to address your other question the wafers basically start piling up in the queue behind that process step. And what is significant about this is when you finally do get the tool back up, you now process a bunch of those lots and effectively have a 'bubble' moving through the fab which impacts areas downstream as well until you finally get that bubble out of the line.

The site experts are generally oncall 7x24 (some may work normal 5x8 shifts or the 3day/4day 12 hour shifts). In 'healthy' areas the oncall responsibility is rotated around. Again this is the second line of defense generally speaking to the FSE's (field service engineers) who are working in the fab (for most areas 7x24)

05 May 2008 04:16


InTheKnow said...
JumpingJack said...
LEAN -- what the heck is this?

LEAN is the latest corporate buzzword for a methodology to improve process flow. It is the basis for the book "Lean Thinking : Banish Waste and Create Wealth in Your Corporation".

Like most other systems of this sort I've seen it seems to go too far. I can easily see this becoming part of a bureaucratic mindset that requires slavish adherence to a system whether it is applicable or not. It originated out of the Toyota Production and Management System. You can read more about it
here.

05 May 2008 04:16


Ho Ho said...
I want this:
"The most amazing is that this machine just cost as a better standard PC, but has 24 cores that run each at 2.4 Ghz, a total of 48GB ram, and just need 400W of power!! This means that it hardly gets warm, and make less noise then my desktop pc."

05 May 2008 06:33


Anonymous said...
"I tell you what - if I were Ballmer right now... I'd threaten to walk away and say 'wow, if he can get such great performance, perhaps we shouldn't take the company oover and then when the stock crashes to the pre-takeover level and crashes again when Yang missed his ridiculous Q2 numbers, Ballmer should step back in and lowball an offer and say "how do you like me now?!?" (comment Apr23)

Fast forward to today - Microsoft walks away from Yahoo deal after the Yang-er thinks his company should have fetched $37/share.

So now instead of getting $31/share (actually MSFT increased it to 33 during negotiations), Yang will have to explain to his shareholders why the stock price is about to plummet to the low 20's. He had conveniently not set a stockholders meeting (so as not to have to answer to his stockholders?)... but I think he is required to do so or face serious repurcussions (I think you can eventually get de-listed). Expect calls for Yang's resignation, calls for election of a new board of directors and a potential avalanche of investor lawsuits.

Expect Balmer to come back in another quarter or two with an offer in the high 20's (though I cannot predict he will say 'how do you like them apples?')

Looks like Jerry Yang just pulled a Hector*

* Hector (from Webster's online)

HECTOR
Function: noun
Date: circa 2006

1: one who screws up
2: botch, blunder
3: one who screws stockholders due to poor decision making and an overly active ego.

Also can be used as a verb, as in he really Hector'd that deal...

I have a new respect for Ballmer on this decision (though I'm not sure where MSFT's SW/OS division is headed).

05 May 2008 08:19


SPARKS said...
“Sparks, I'll take a stab at your questions:”

Thank you, excellent, that puts a lot of the pieces together. Especially with the above mentioned single flow (?) vs. batch operations discussed above.

“Here in lies the beauty of Intel's copy exactly approach - when you ship the lot to another fab, you know that tool is setup identically to the fab you are shipping from and will get identical processing.”

Whoa, great observation, one that didn’t occur to me, anyway. This seldom, if ever, is mentioned in the ‘pros and cons’ of the ‘copy exactly’ debate, probably because a lot of people wouldn’t get it anyway. Nonsense, with this kind of flexibility, personally, I think it would be stupid to take any other approach. Standardization of components has been the corner stone of HV industrial production for over a century.

I saw the test structures that are sacrificed when the wafer is cut here. I’m sure there are propriety methods to insure quality control at the very early stages of production. If there isn’t, there ought to be. Additionally, I’ll bet there’s a fixed dollar amount, determined by the corporate bean counters, cost wise to get a single wafer through the snake. Going down the entire line ain’t cheap, and a wafer is a terrible thing to waste.

http://www.tf.uni-kiel.de/matwis/amat/elmat_en/index.html

(Great site, by the way.)

This led me to a few more links where I found pictures of the vertical furnaces that heat the wafers in vertical batches. They looked huge, complicated, and expensive. I figured on the redundancy aspect to keep thing moving while repairs are made on the tools that go down. Some of the HV units queued up a number of FOUP’s as part of their specifications, as apposed to the lower volume R+D units. Given Dementia’s single flow argument and AMD's current execution, it may be to AMD’s advantage to stay small.

“The site experts are generally oncall 7x24 (some may work normal 5x8 shifts or the 3day/4day 12 hour shifts). In 'healthy' areas the oncall responsibility is rotated around. Again this is the second line of defense generally speaking to the FSE's (field service engineers) who are working in the fab (for most areas 7x24)”

I can see (and I know) that this is a nice position to have, especially if you’re a really good trouble shooter who has an intimate working knowledge of the equipment’s guts. I’d bet my shares in INTC these guy’s are “crackerjacks”, and the outstanding guys are really in demand. There’s lots of glory to be had when things are up and running quickly. Pressure, adulation, heroics, instant reward, for me this is an enviable position. I love glory; that’s me, guts and glory.


“Well the managers pester the engineers or ops people who then pester the technicians who are working on the tool.”

I was right; they are poor bastards. Obviously, Silicon rolls down hill, too.

Thanks again, (sigh) maybe in another life.

Very enlightening.

SPARKS

05 May 2008 13:29


SPARKS said...
"Fast forward to today - Microsoft walks away from"

You said it. That was the first thing I thought of when I read the anouncement. Time to DUMP!!!! Yahoo.

SPARKS

05 May 2008 13:44


Tonus said...
ho ho, that helmer site is awesome.

05 May 2008 13:46


Comment deleted
This post has been removed by the author.

05 May 2008 16:58


Giant said...
This is interesting.

Although, I haven’t had the QX very long, nor have I explored it's absolute limits, I have found the same VERY comfortable point at 4.06 GHz.

Yes, around 4GHz is perfect for the 45nm CPUs, both dual and quad (aside from the lower end quads that wouldn't hit 4GHz due to a FSB limit). Obviously the QX9650 and QX9770 are premium parts and are binned accordingly, so the power use is low and not all that much higher than my E8400 at ~4GHz. With a TRUE 120 equipped with a Scythe S-Flex fan the temperature under a full load has yet to exceed 50C.



I have, however, found the limit for air cooling:

From CPUz:

9.5 x 450= 4.275 GHz @1.408V, 1800 FSB, DDR3@1800 7-7-7-21 2T 2.0V

Sandra:

Processor Arithmetic= ALU 66835 MPS, SSE3 = 61753
Processor Multimedia= 549144 it/s, FP=267068
Memory bandwidth= 9576 m/sec!
(Now it’s clear why I waited for X48)
Cache + Memory Combined=65.47 G/s
32K blocks= 407 G/sec!
Latency=56ns
SuperPi 1M= 10 seconds!!!!!!

Obviously, both chips run cool (yours and mine) and there’s A LOT of headroom (a full GIG!), basically, on first production run. Binning these chips (?), man with the way these thing run, it’s a shame to deliberately lock in anything below 2.6. It looks like INTC doesn’t have very much to throw away.


I suspected INTC months ago sandbagged these chips when Barcelona fell on its ass. They were ready for Barcelona even if the son-of-bitch comfortably hit the 3 GHz+ speeds they were howling about for a year. It simply had no chance, ever, against Penryn, right out of the gate. Look at that Pheromone at 3.5 Gig, a cherry picked slab. The QX9770 s pee’s all over it at well bellow stock speeds!

The Phenom was cherry picked, and wasn't even stable at that speed. Eventually he settled for 3.4GHz with 1.58V! This would not be acheivable with air cooling. Constrast that to you and I both running these hafnium infused monsters at 4GHz+ on air! In terms of what Intel could release now, assuming a 1600FSB, I predict that 3.4 and 3.6Ghz for quads would be possible, and up-to 3.8GHz for dual core.

I don’t give a flying hoot what anybody say’s. INTC woke up and hit the floor running. If they don’t believe it, you and I have the evidence in hand to prove it.

E8400 @ 4 Gig
QX9770 @ 4 Gig

WITH NO MEANINGFULL DIFFERENCE IN THERMALS AT THESE SPEEDS!

That's right! The power consumption on this puppy is incredibly low at stock. Even overclocked to 4GHz the power consumption of the CPU is only around 100W, that's easily cooled with high end air. Obviously, at 4.5Ghz and beyond we're pushing the CPU to it's limits, so the power consumption is too high for 24/7 use without water IMO.

BTW: With all these runs, I haven’t had a lockup, boot failure, BSOD, or a failed Windows load, yet!


I've had one lockup, that was when I tried to reach 4.5GHz on the P5B deluxe. The northbridge was just running too hot for a 2GHz FSB. As I described in an earlier posting here, I attached a 40mm SilenX fan to it and that reduced the temperature considerably, I had no problems after that. The 790i has been a SUPERB board to me, I've had no issues; none at all.


I’m going to back this gem down to 4 Gig and cruise around nice and comfortable 24/7, all on air.

What sort of bus speed are you running there, and what speed are you running the DDR3 at? As I've mentioned before, 1780MHz works perfectly for me. A beautiful 4GHz clockspeed, 1780Mhz FSB and dual channels of DDR3 at 1780MHz a piece!

-GIANT

05 May 2008 17:03


SPARKS said...
GIANT-

If there's any doubt about the lack of consistent quality of these chips, the entire line up, their speeds, and the way they overclock, this should dispelled them without any reservation.

E8300
E8400
And the currently on sale mega bullet,
E8500@3.16 (I’m was tempted to buy one these sweeties for shits and giggles)

They all clock, and clock well! Really, think about it, INTC’s standard on binning these things must be pretty high before they lock in those multipliers. It makes you wonder, if the relative price structures are based on feature sets, as apposed to speed bins. INTC is only competing with itself here, especially with a dual core solution.

When INTC revealed 45nM hafnium transistor technology as the biggest improvement to twenty years, generally, the Press reception varied from a yarn to beer fart. What the knuckleheads fail to realize, this process will be the foundation for the next generation architecture with an IMC pumped in. Imagine these chips on steroids? Man the thrill is back, big time, and the hits just keep on coming.

As far as my setup is concerned, overclocking this GEM was painless and a no brainer.

From CPUz :

9.0 X 450= 4050 MHz

Vcore 1.3975

On this board you set the memory parameter @ “*DDR3-1800 O.C.*
You set the option to allow the “memory strap to FSB” and you’re done!

450 quad pumped at the Memory will give you DDR-1800; again this is all factored in by the MOBO automatically. Everything is running synchronous, just like I like it.

So much for the idiots who complain about the high prices for premium MOBO’s, F**K ‘em, ya get what you pay for I say, in spades.

Besides, I used to spend a lot more money on things that could have got you thrown you in jail, and that includes booze! That said, what’s an extra 150-200 bucks? That’s used to be one night out in a club, easy, when 200 bucks meant something!

The SuperTalent ‘Project X” DDR-1800 memory gamble I took for $379 paid off huge. At these speeds it’s cold, not warm, not cool, just drop dead cold. (After the CPU cold water solution, I may purchase another set. However, stability concerns surface when running 4 discrete DIMM’s at high speeds, as opposed to two 2 GIG modules.)

I set the timings manually at the manufactures recommended 7-7-7-21.
The voltage was manually set at the recommended 2.0V

Speeds any higher will necessitate looser timings, 8-8-8-24, give or take, on any individual parameter, stability dependant, when locking in the *DDR-2000 O.C* option in the BIOS.

I’ll trade a few nanoseconds in latency for the looser timings and higher speeds. I haven’t gone there ---- yet.

ALL said, this 4 GIG synchronous solution was basically a no brainer. And to think, last year, I was plodding along at 1066 FSB. Now, that’s what I call leaping ahead.

SPARKS

05 May 2008 19:31


Anonymous said...
"Additionally, I’ll bet there’s a fixed dollar amount, determined by the corporate bean counters, cost wise to get a single wafer through the snake."

I've been involved with some cost modeling, and while there are generally specific cost targets (per wafer processed), I've come to the conclusion that it is impossible to measure accurately. There are simply too many fixed cost (building cost, equipment) and costs which are shared by the entire fab (fabwide facility costs, metrology, automation, service, headcount...) that are as significant if not more than the true variable costs (actual Silicon substraate, chemicals and gases, waste, etc...). So the best you can do is have a modeled/average #.

As for the VDF (vertical diffusion furnaces), surprisingly they are no more expensive than an average piece of fab process equipment.

Finally copy exactly has it's downsides too - once you enter volume manufacturing it pretty much discourages many changes as now you have to proliferate that change across a huge fleet of tools. Though some would argue that is exactly what you want when you enter the manufacturing stage - minimal risk, and only insert a change if there is a huge ROI. For engineers (and suppliers who want to implement their latest and greatest changes) it is disheartening but one minor screwup in terms of implementation of a change and it quickly kills the benefit the change had in the first place.

05 May 2008 20:42


Anonymous said...
One add:

"As for the VDF (vertical diffusion furnaces), surprisingly they are no more expensive than an average piece of fab process equipment."

And this is the fundamental problem with the whole single wafer processing move. Sure single wafer processing has some cycle time advantages but when you consider the furnaces (or you can also look at the wet etch benches too) cost as much as single wafer equipment but may have as much as 2-5X the output capability per capital dollar spent, what would you do?

05 May 2008 20:49


SPARKS said...
"I've come to the conclusion that it is impossible to measure accurately"

Coming from you (?!?!), that’s saying something! Kudos for even giving it a shot! I’ll bet it took months.

"Though some would argue that is exactly what you want when you enter the manufacturing stage - minimal risk."

"cost as much as single wafer equipment but may have as much as 2-5X the output capability per capital dollar spent, what would you do?"

Factoring in these two comments, I’ll answer your question; I'll tell you exactly what I did and what I am going to do.

1) Buy a $1500 behemoth-----done!
2) Buy some more INTC------ this week!


I love INTC’s conservative approach, “minimal risk”. I’ve seen too many loose cannons, screw up too many times, reinventing the wheel midstream.

SPARKS

05 May 2008 21:33


Anonymous said...
This "LEAN" is old news. I work at an Intel Fab and we've been using this for several years already. We call it something different but it's basically the same thing that Toyota started "Kaizen" awhile back. I personally think that on paper the whole concept looks great but in real world practice it is not that practical. Just makes management think that they have a better control of the floor.

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