1.11.2008

AMD delays Phenom because of pesky bugs customers

AMD admits to recent rumours that higher speed Phenoms (9900 and 9600) will be delayed until the second quarter. Luckily for AMD, nobody waits for mid-to-low-end CPUs. So except for a few people at AMDZONE, nobody is really disappointed by this news. AMD vehemently denies that the delay is due to the TLB bug found back in November. “The B3 stepping is not bugged”, according to INQ reporter Charlie Demerjian after speaking to AMD’s Pat Moorehead. Pat Moorehead is the Executive VP of Marketing at AMD who is coincidentally also running the Barcelona Debugging Task Force. If we can take the word of an AMD executive then the company should now be focusing on understanding why their process is producing energy efficient chips instead of 9900 Phenoms.

Energy efficient chips are what our customers want, declares AMD, which is very fortunate because this is all they have anyway. Either this is a profound coincidence or AMD is confusing desktop with OLPC demand. Phenom 9900 and 9600 will be pushed out until next quarter because AMD is now trying to meet the ‘unusual’ demand in this low margin segment using nothing but very expensive parts. While some analyst believe that such a move is void of any logic, some would argue that at least AMD isn’t throwing the CPUs away like McDonald’s with their silly 15-minute rule on burgers. (But if McDonald’s goes into financial trouble and tried to sell cold and stale burgers because they insist it is what the customers what, it would just be pathetic).

Similar to how the tri-core Phenom is targeted at the tiny tetraphobic market in China, AMD believes that there is a healthy market out there for expensive energy efficient processors. Well at least until they figure out a way to fix Phenom.

44 comments:

Giant said...

BOOT DAILY'S WORST TEN TECH PRODUCTS FOR 2007:

http://www.bootdaily.com/index.php?option=com_content&task=view&id=972&Itemid=56&limit=1&limitstart=3

No surprise really, AMD Phenom made #3 on the list!

3. AMD Phenom:
With a name that's short for "phenomenal", one would think of a product that sets the bar for performance, power and pricing; yet AMD's release of its Phenom CPU in December proved to be to contrary to that thought. Over the past 12-18 months I heard AMD fanbois make snide comments at Intel's Core2Duo platform such as "but just want until AMD releases quad-core because at least it'll be a true quad-core" – blah blah blah.

Well it's out now, it gets slaughtered by Intel in every benchmark and clock for clock it's a complete waste of money. I was hoping for at least a horse-race but instead we end up with a blood-bath in favor of Intel.

Motherboard chipsets for this chip are really behind the 8-ball and until NVIDIA's nForce 700-series starts shipping for Phenom, there's little hope it'll catch on in the enthusiast market – at least in a way that can help pull AMD out of a financial downward spiral.

Anonymous said...

From http://www.overclockers.com/tips01277/

What was far more interesting was AMD saying that there would not be any further 65nm steppings. Whatever we get in May or June or whenever is it. AMD doesn't apparently plan to slog its way through to higher speeds like it did with the X2s.

The next K10 stepping will be the first 45nm chips. While there may be, probably is, excellent reason to move on from 65nm, keep in mind that the first of these chips won't show up for sale until September at best, and wouldn't become plentiful/cheap (unless they're really slow) until 2009.

Yes, it's a "damned if you do, damned if you don't" situation, but it only goes to show what a deep hole AMD is now in.

S said...

Each process change demands huge investments retooling the factories. If AMD is planning to leave all its problems to be solved till it moves to 45nm, their 65nm investments would have barely have had any return on investment as their 65nm products haven't really been selling. AMD will have to borrow heavily again to get their factories going with 45nm.

For me, whenever they have spoken about thier 45nm plans , I felt they are speaking wishfully rather than with anything concrete planned.

Anonymous said...

"If AMD is planning to leave all its problems to be solved till it moves to 45nm, their 65nm investments would have barely have had any return on investment as their 65nm products haven't really been selling."

Keep in mind a few things:

1) AMD will be selling 65nm X2's for a WHILE - yes I know you have the fanboy ridiculousness of fast product conversion ramps but this doesn't happen in the real world. These will likely be produced well into 2009.

2) They will also be producing 65nm K10 dual cores (I think?) which will be significant volume.

3) Mobile anyone? There is no K10 mobile part, 65nm will likely crank these out for a while until they can get a power savings on 45nm and convert mobile to 45nm (mid-2009?)

4) The B3 stepping will still sell in server and perhaps in desktop world - there is still a market that will choke down the underperforming chips (whether it's the upgrade folks or the I only buy AMD folks or the I only care about price folks)

5) The conversion to 45nm will reuse a significant (probably >70%) of the 65mn fab equipment. This is true of most tech node conversions. There is not a whole lot of new equipment for AMD on 45nm - you have the immersion litho tools and some tools in the backend related to the ULK film.

6) The conversion to 45nm will take some time, if parts start coming out at end of 2008, that means you will have 65nm parts likely throughout 2009. As they started selling 65nm parts in Jan'07 this would be 2.5-3 years which isn't too bad.

So the tooling will not be wasted, the problem for AMD is that their relatively 'new' technology node will only be able to sell discount parts. So they were not able to get the margin benefits you should get from a tech node conversion because they've been forced to slash prices to remain competitive.

In hindsight they would have been better from a cost perspective just to have cranked out the smaller die K8's until K10 was truly ready rather than trying to save face and waste all the time, money, and credibility of paper launches, soft launches, re-launches, and energy efficient launches... this responsibility should fall squarely on Hector Ruiz! Yes you can say the engineers and/or manufacturing folks didn't execute to plan, but someone should have said does it make sense to launch this solely for PR? I'm sure marketing was pushing for it, but the CEO should be the final call and ultimately he chose to attempt to manufacture a part and sell it WHILE trying to fix it instead of delaying it, getting it right and then launching.

Anonymous said...

Did I read your blog right? The VP of MARKETING is running the Barcy debugging task force?

WTF! Is this really true? Is he heading their process development too? Because that would explain a lot of things to me!

SPARKS said...

You know, somewhere, way back on some prior posts, months ago, I can’t help but think of GURU’s, very cautious, “speculation, on my part”. I don’t know if you all recall, but he did predict, at the time, they would ever get this dog to ramp at significant speeds.

Man, did he nail this one, B1 B2 now B3, b4 and after, I suspect no mater what the hell they try with this thing, it ain’t gonna fly! Every time the ‘new and improved’ Barcelona is released and tested, and it then falls flat on its ass, I say to myself, “man was he right!”

Alright, GURU, where are you, get your head out of the transmission electron microscope, or some future esoteric process theory and analysis, and throw the minions on ground level a bone. What’s going on here? What’s AMD up against, from ground up?

Look, you had your suspicions from the onset. Now that your suspicions have been confirmed, once, twice, now thrice, get out the crystal ball, what you see, oh GURU?

Architectural?
Process?
Both?

PS Orthogonal, you sly dog, don’t give away company secrets or anything, but can you tell us what the feelings of Barcelona are on the “Intel Inside”?


SPARKS

Anonymous said...

I now think a good chunk of K10's issues are process related and I'm sticking by the thoery that the whole TLB mess was a convenient means to HIDE the other issues (like many AMD fans, even though I'm not, I don't think the TLB is that big a deal- except maybe in critical server applications).

I think the decision to make B3 the last stepping for Phenom quads is acknowledgement that there were no massive benefits via stepping to be had (no new steppings = no more design changes/tweaks on 65nm), so to me this is a 65nm process issue, specifically as I have said before a power (leakage) issue. Though you may see AMD squeeze another bin out of 65nm in H2'08 as they continue to tinker and improve the process. It seems like they are hoping 45nm through the lower active power (lower threshold voltages --> lower Vcore --> lower active power) will help in this area but as myself and JJ have pointed out leakage will grow on 45nm, especially with no change in the gate oxide and the normal increase in subthreshold leakage (leakage from source to drain when transistor is off) as geometries shrink.

The other telling data point is AMD's "decision" not to replace the higher clocked dual core 90nm K8's with 65nm counterparts when 90nm is EOL'd. They are either doing this out of fear that they will be similar to the eventual dual core K10's in performance or they simply can't get the clocks that high on 65nm in an acceptable TDP window. K8 is a PROVEN architecture so unless this is a marketing decision, it points to 65nm process issues or AMD incompetence with the dumb shrink from 90nm to 65nm (which I don't think is the case).

It is difficult to say if there is an architectural issue with K10, as I think the clocks are so low, and power high enough that it is impossible to see any design issues until these are fixed (the old peeling the onion metaphor comes to mine). Once AMD gets a handle on power (leakage), they will be able to clock better and then we'll be able to see if there are any design issues.

I think I did say a 2.6GHz by end Q2'08 with a shot at 2.8GHz.... so even I may have been a bit optimistic. 45nm will not be much better as leakage issues will continue to dominate - it will help AMD economically (smaller die size), but at best 45nm will yield 1 bin over 65nm LONG term. Early on 45nm will likely release at or below 65nm clockspeeds as many on this blog have predicted.

On a positive note, I do think AMD will be able to get respectable clocks on dual core K10's though (~3-3.2GHZ maybe). Though it seems like this won't be until H2'08, unless AMD hits a home run with it's initial dual core K10 release which I think is sometime in Q2'08. Though I wouldn't be surprised to see an "energy efficient" dual core release at first, because I hear that's what people are demanding! You know we could get the clocks up but we are customer-centric.... and if you believe that one I have some really cheap stock to sell you!

Anonymous said...

Did I read your blog right? The VP of MARKETING is running the Barcy debugging task force?

WTF! Is this really true? Is he heading their process development too? Because that would explain a lot of things to me!


lol. i think he was joking. sort of throwing back the credibility of AMD management when it comes to say anything... especially a marketing guy talking about microarchitecture bugs.

Orthogonal said...

PS Orthogonal, you sly dog, don’t give away company secrets or anything, but can you tell us what the feelings of Barcelona are on the “Intel Inside”?

A little bird on my shoulder just told me that...

*GETS SHOT*

InTheKnow said...

Speaking of being first to market. Some initial impressions of Silverthorne MID's are in.

All in all they don't seem to be too complimentary. I'm hopeful the poor performance is due to the units being pre-production prototypes.

My concern is that this might be an indication that Silverthorne isn't up to the job it was intended for.

giant said...

One can't help but admire this t-shirt:

http://www.legitreviews.com/images/reviews/645/intel_phenomenal.jpg

Poor old AMD!

Anonymous said...

'Speaking of being first to market. Some initial impressions of Silverthorne MID's are in."

Yeah I think the first generation of devices will likely be trial balloons to shake the bugs out of the devices. I'm surprised to hear about a 30GB drive on one of them - I thought/was hoping these would have flash based HD's (which would be more reliable and potentially use less power). Also I'm stunned to hear one was running Vista - I wonder how much RAM it had! I'm not surprised it was unresponsive with a 1.2GHz CPU, and likely a bare bones amount of RAM.

SPARKS said...

“It seems like they are hoping 45nm through the lower active power (lower threshold voltages --> lower Vcore --> lower active power) will help in this area but as myself and JJ have pointed out leakage will grow on 45nm, especially with no change in the gate oxide and the normal increase in subthreshold leakage (leakage from source to drain when transistor is off) as geometries shrink.”

“I think I did say a 2.6GHz by end Q2'08 with a shot at 2.8GHz.”

Yes you did. And said you were being conservative, and you expressed doubts.

OK, as you and JJ have been pounding, the leakage issue, especially subthreshold leakage (Isub??). Obviously, as you explained before, this issue has dogged them since day one.

Why the hell then, would they expect miracles at 45 when the thinner layers increase the leakage, but lowering the voltage would decrease the leakage. It sounds like a dog chasing his own ass, only this time they made a smaller dog, so they’re gaining nothing. So they can get him to spin around a little faster, but it is still the same dog, just 10 to 20 percent more of them. Big deal why bother----unless.

Could it be possible they are sneaking in a new process variable such as INTC’s hi-K. Is that possible with their current process; could it be done? Do they have the tooling for it? Could their silent partner, IBM, help them through this ordeal? Can they teach this old dog a new trick, so to speak?


PS Orthogonal, “GETS SHOT”, GETS HOT? Shoot myself? Say What????


SPARKS

Anonymous said...

'Could it be possible they are sneaking in a new process variable such as INTC’s hi-K. Is that possible with their current process'

It's theoretically possible, especially with a gate first process like IBM's which has fewer changes, but even then there are still dramatic impacts. The High K / metal gate affects a lot of your transistor variables that are carefully targetted by many process steps. If you simply swapped in high K, your threshold voltage for your transistor (the voltage that has to be applied to the gate to turn on the transistor) would likely change which means a few of your critical implant steps would need to be re-targeted (and then potentially your implant anneal). Also you would need to change the process that etches the gate oxide as you have a different film and the etch that does the poly patterning as you now have a metal to etch as well (BTW, metal etching is generally a dirty process and could have a significant yield learning curve depending on the metal). These are a few examples - none of these would mean new tooling but would require a lot of development.

Also a change like this has impacts to the CPU reliability, meaning a vigorous re-certification/burn-in testing. Accelerated lifetime testing, thermal stressing, voltage stressing etc... this would not be like a CTI step where you could get away with a subset of this testing. There is nothing saying you can't do this again mid-process node, but why would you want to? This is expensive, time consuming and sucks down additional resources.

As for tooling it is hard to say, my bet is that with the gate first process IBM is going with an MOCVD (chemical vapor deposition) process as opposed to Intel's atomic layer deposition (ALD) process. MOCVD equipment is far more mature and a known quantity, so there is not as much a learning curve as ALD, and could rapidly be installed.

It would seem to be foolish to do this mid-node, it's essentially like doing a whole new technology node transition. Sure you could theoretically do it but why given the risk, resources needed and costs? In my view it would be better to simply delay 45nm to intercept this if it is that close or push the change out to 32nm. Keep in mind, even if implemented on 45nm, it will need to be re-tuned and re-optimized on 32nm again anyway so it's not like the whole (bogus) immersion argument of well we'll need it eventually anyway and we'll be further ahead on the learning curve.

And if your question is asking could they sneak it in at the beginning of 45nm (which is theoretically 'ramping' right now according to AMD) - I don't think so, this would likely have leaked worse than an AMD 65nm transistor by now. AMD would also have likely made a big deal of PR on this given the state of their stock and their need for good news.

Anonymous said...

'Why the hell then, would they expect miracles at 45 when the thinner layers increase the leakage, but lowering the voltage would decrease the leakage.'

I don't think AMD expect miracles, I think it is mostly fans and/or press who lack the scientific background and assume new node = better. My guess is AMD is doing this mostly for economic (smaller die size) reasons. I also don't discount the Ruiz ego factor (we're catching up, this will give us more capacity to get to 30% market share at all costs... etc)

Keep in mind with power you have several components. The active power is helped by the lower Vt because the Vcore (this is the power that you see on CPU-Z) required is also lower. The Vcore is set above Vt and the amount of 'overdrive' is one of the determinants of switching speed. So you can lower Vcore with the Vt in step so you consume less active power or you can hold Vcore and theoretically get more clockspeed because your overdrive is greater (this is effectively like OC'ing the CPU).

The problem is the lower transistor Vt's also INCREASE the subthreshold leakage (Isub). You can think of it this way - as the lower the Vt becomes the closer the transistor is to being in an "on state" even when it is off and you are therefore more susceptible to leakage between the source and drain of the transistor.

Then you have the gate leakage which I think folks are familiar with. You also have junction leakage to the substrate which is what SOI addresses but this is a distant third in the leakage impacts.

Almost everything in the front end is, sadly, a tradeoff - things that help switching speed often increase leakage and vice versa. However innovations like strained Si and high K, have given 'free' improvements. I say free because you gain performance while not significantly negatively impacting other key variables. Of course the 'non-free' part is the added complexity and cost of the new processes.

So when Intel announced both a Isub and Igate leakage improvement with the high K process.... it really is only the Igate that is directly addressed by the high K. However the ability to scale the oxide (because of the higher K and lower leakage) meant that Intel was able to gain switching speed too, which means they likely retargeted some of the other processes to help Isub. So indirectly the high K was responsible for it...as without it the other changes would not have been possible.

Orthogonal said...

sparks said:
PS Orthogonal, “GETS SHOT”, GETS HOT? Shoot myself? Say What????


Lol, it was just a joke.

Anyway, what I really mean is, I honestly don't know anything more about what Corporate thinks about Barcelona than you do. That type of information doesn't waterfall to the peons since they don't want a nasty fallout if some goober says something stupid or misunderstands/misrepresents something in Intel's name.

All I ever hear is what you would expect from any company "Don't get complacent, work hard, execute as if the competition will make good on it's promises, etc..."

Anonymous said...

I also would expect AMD to not scale the gate oxide at all on 45nm (The SiO2 solution was effectively at it's limit on 90nm) which is why I don't see much performance gain either. AMD is tweaking other areas to get some performance (for example increased strain), but this is relatively minor compared to other past tech nodes changes.

AMD's big choice is with the lower Vt on 45nm do they lower the Vcore by the same amount? If they do they'll see very little clockspeed gains (if any), but the lower active power will potentially offset the increased off state power (via leakage) which will mean they can maintain or perhaps even lower the TDP's on 45nm.

If they lower the Vcore by less than the amount the Vt is lowered, then they are effectively overclocking (increased overdrive) which would theoretically give them more clockspeed. The problem with this is you now have increased leakage from both the lower Vt AND the increased overdrive. It is questionable whether AMD could do this and keep their TDP targets, unless they made improvements in leakage somewhere along the line... or make 'improvements' to their APC (average power consumption) metrics!

Below is a link with a good picture (top right graph on page 3) of active power vs offstate power. It is a bit dated as it assumed ever increasing clocks through 65nm which is why you see active power still going up - in actuality this has turned around and is now decreasing. (This was based on the P4 model)

http://www.sigda.org/Archives/ProceedingArchives/Dac/Dac98/papers/1998/dac98/pdffiles/44_2.pdf

It also shows the impact if you did not scale Vcc (effectively Vcore) and the increasing offstate (leakage) power.

SPARKS said...

“none of these would mean new tooling but would require a lot of development.”

“This is expensive, time consuming and sucks down additional resources.”


“It would seem to be foolish to do this mid-node, it's essentially like doing a whole new technology node transition”

Well, GURU, as usual, you’re in good company (or they are in good company, subtle, but true). The article doesn’t backup this statement with your in depth technical prowess, however, which is what I was looking for, by the way, thank you.

“the resources the company might expend squeezing an extra speed grade out of K10 might well be used more effectively elsewhere.”

http://arstechnica.com/news.ars/post/20080110-amd-pushes-phenom-9700-into-q2-preps-low-power-variant.html


“a few of your critical implant steps would need to be re-targeted (and then potentially your implant anneal). Also you would need to change the process that etches the gate oxide”

Recently, last night as a mater of fact, I had an emergency building shutdown (partial). A 480V/277V, 800A fuse burned in its holder, and finally blew. The director of property operations asked, “Why don’t we install a larger fuse” Sure, I said, let’s redesign the main distribution feeders (more feeders, 20 floors down), remove this equipment, install a larger distribution board (1000A), and re feed the entire 4 floors. His reply, “can you do this tonight?”

GURU, that’s when I need the Valium. I hate it when laymen think you can simply change one part of the designed system without changing the all the variables in the system as a whole. Further, it easy for me, I’m not limited to 250 sq. mm, my stuff is big and in your face.

In any event, thank you, I will reread your excellent analysis.

SPARKS

SPARKS said...

“ which means they likely retargeted some of the other processes to help Isub. So indirectly the high K was responsible for it...as without it the other changes would not have been possible.”

Again, to reiterate my last post, thanks again for the further detail. I’ll look at it more closely.

SPARKS

SPARKS said...

“I honestly don't know anything more about what Corporate thinks”

F**K corporate! I was talking about the guys in the trenches. You once mentioned some of the old timers felt that the tide was turning and the feelings were they were back in the groove again.

“All I ever hear is what you would expect from any company "Don't get complacent, work hard”

Don’t think you’ve got a monopoly on this one. I could be turning a 35% profit on one of my jobs, and they’re still looking up my ass.

It was nothing specific. Just how are those guys feeling now about AMD’s present process quagmire GURU, so eloquently, put into a few short paragraphs above?

SPARKS

Anonymous said...

I like arstechnica in general but the article at times seemed more cheerleader than anything else....

"Toliman could potentially be an enticing upgrade path for K8 owners on Socket AM2, especially if the new CPU line debuts at dual-core price points."

I think the assumption, as mentioned later in the article, is that the tri-cores are going to magically come out at high clockspeeds (they won't). Why would they? This whole misrepresentation by the media of being able to disable a "slow" core and thus magically raise bins is not reality. You simply don't have that much fmax variation over a small distance (on the order of 10mm)... you may get a bin as you can raise Vcore as you have one less core and can still maintain the TDP bin, but it's not like you are going to get 3 or 4 bins on the tri-core chips.

Even Ars acknowledges this, so why would they say it could be an enticing upgrade plan... they might as well say if the B3 stepping comes out at 3.5GHz it will do really well - yes the comment is technically accurate, but how likely is it? And AMD is going to price a tri-core chip that takes 2X the die area at the same price as a dual core and not charge ANY premium - sounds like more sound financial planning from AMD.

"Rumors have also surfaced that the company won't ship 45nm parts in volume until early 2009."

Phil Hester (CTO of AMD) stated this - this is hardly a rumor!

http://www.mercextra.com/blogs/takahashi/2008/01/08/ces-live-deans-tuesday-experiencemeeting-with-amds-phil-hester/

I'm also not sure exactly why people are expecting large freq increases with B3... fixing the TLB bug does not make the chip clock faster (it eliminates the performance hit of the BIOS fix). Unless AMD is doing more changes than the TLB fix, B3 isn't going to be much better.

I did think the conclusion was dead on - if you are significantly behind, marginally reducing this deficit by a single speed bin is not worth the effort...

Anonymous said...

'AMD spokesman Jake Whitman said that AMD's "OEM customers are placing more priority on our energy-efficient and triple-core processors, where the volumes and ability to differentiate products take precedence over the more prestigious, but much lower volume, higher performance quad-core products.'

From TGdaily. Yeah we all know the energy efficiency focus is a bunch of crap... but now performance is characterized as "prestige" , interesting spin on things... AMD is coming closer to my prediction of the "good enough" marketing campaign. Good enough = commodity parts = low margins = we give up.

Funny if they want volume and energy efficiency why not churn out dual core K10's first!?! Perhaps because the clocks on those also suck and would have to be priced at bargain basement prices?

The tri-cores take up twice the Si space as the dual core K10's will...is AMD going to get 2X the price on the tri-cores? Call me a conspiracy theorist but I'm going to throw a couple of ideas out (pure speculation)

- AMD has a ton of non-working quads that they are trying to pawn off as tri's. I really do not think they would disable working cores as the tricores will be lower priced than the quads but have the same cost. This differentiation is a bunch of crap! If it is differentiated then they should get a premium for it! Why would you choose to sell something at a lower price (tri-core) than a higher price (quad core)? Oh yeah customers are demanding it!

- does the dual core K10 have issues with clockspeeds? If so they would have to slash prices really low, which would have a compounding impact on K8 as those would then have to be cut too. If these things don't come out at or above 3.0GHz (top bin) then you potentially have your previous generation chip on an even older technology (90nm) offering higher performance! (this may also be an alternative explanation to why there was no K8's on 65nm that replaced the 3.0 and 3.2GHz 90nm chips!)

Could you imagine the PR hit if the top dual core bin was say 2.6GHz? Our next generation, 65nm chip can't keep up with an older technology, older generation (90nm) chip! I'd like to see AMD try to 'energy efficient' spin that!

Roborat, Ph.D said...

excellent summary gutterat.
How did we get here?

it's a good reminder just before earnings week.

GutterRat said...

Roborat, Ph.D, wrote,
excellent summary gutterat.
How did we get here?

it's a good reminder just before earnings week.


Thanks...I wish I had more time to blog and you've been doing a great job keeping the conversation going!

I noticed that The shiny silver one, abinstein and others have gone into exile on AMDZone.

Also, Circus Maximus, aka Sharikou, the tool's blog seems to have turned into a cesspool.

Are people still refraining from posting on The Managing Editor's blog? Things there don't seem any better either.

Ho Ho said...

"The tri-cores take up twice the Si space as the dual core K10's will..."

I'd say that dualcores are at most 1/4 smaller than quads. Remember that shared L3 still exists with duals and I doubt that crossbar and NB get much smaller.

S said...

Remember tri-cores are the silicon which would be trashed if there is no tri-core. So any revenue out of these bad dies is a plus.

If AMD is confident of ensuring a supply of bad dies, that means their current process has die yield problem which is generating lot of dies with one core dead. This is not such a good thing.

Tonus said...

I get the feeling that this is the end result of the push for market share above all else. OEMs will take and sell those tri-core and quad-core Phenoms, but only because they are available for less.

It's possible that AMD will be able to sell lots and lots of Phenom CPUs and possibly even grab more market share while still losing money, because they have to undercut Intel pricing in order to generate sales.

Perhaps in a month or two Sharikou will once against boast about how inexpensive AMD CPUs are, compared to Intel CPUs. Which is great for consumers out for a bargain, but not so great for AMD since they have nothing at the high-end to provide some useful ASPs.

Anonymous said...

'I'd say that dualcores are at most 1/4 smaller than quads. Remember that shared L3 still exists with duals and I doubt that crossbar and NB get much smaller.'

Overall L3 amount is smaller for the duals, you have fewer HT links, bt yes you are correct the dual cores wont be half the size due to northbridge being need on both.

My point is people are saying tricores will help AMD because they will be able to sell them at a higher price than dual cores but if you can make nearly 2X (or 1.7X) the # of dual cores on the same amount of Si, unless you are getting that same price increase tricore is less profitable.

SPARKS said...

It makes you wonder what those jackasses at B.O.A. and Morgan Stanley are smoking when an earnings preview like this pops up. Duh.

http://news.moneycentral.msn.com/ticker/article.aspx?Feed=AP&Date=20080114&ID=8035459&Symbol=INTC

1.09 0n the day. I suspect the real meat and potatoes will come shortly. I can't wait to see the margins and record sales.

SPARKS

SPARKS said...

I've just about had enough of Charlie D. horseshit concerning Barcelona. I can't believe the INQ printed my comment.

Thanks to you guys, it really sounds like I know what I the hell I’m talking about!


http://www.theinquirer.net/gb/inquirer/news/2008
/01/11/barcelona-b3s-fine

SPARKS

Anonymous said...

'Thanks to you guys, it really sounds like I know what I the hell I’m talking about!'

not bad... you should throw in gate leakage in with the Isub next time as they are comparable on 65nm.

Also you forgot to ask Charlie about his RIDICULOUS argument of Intel possibly developing 2 45nm processes because the initial process was not healthy!

SPARKS said...

Hey, easy there wrangler I’ve just come to grips with the On/off threshold state, as I’m still digesting the gate leakage issue, while I reread the posts and do some private investigations.

By the way, I gave the 45nM thing as pass. It was, in fact, so ridiculous; I didn’t want to qualify it with speculative response.

However, it seems the Xeon 5345’s just went over the top in the server space. Leap Ahead, with nuclear control rod metals.

http://www.worlds-fastest.com/wf2400.html

SPARKS

Orthogonal said...

Hey, easy there wrangler I’ve just come to grips with the On/off threshold state, as I’m still digesting the gate leakage issue, while I reread the posts and do some private investigations.

Sparks, if you're really that interested in Semiconductors like we all know you are, you should buy some used textbooks and read up. Start off with CMOS Device Physics and then move on to the Silicon Processing and Integration books. They don't even have to be that new, the old texts are still a great intro into the field and can be found very cheap, and then you can follow up with some of the newer submicron specific texts.

SPARKS said...

Well, thanks, but what you guys bring to the table is a practical hands-on approach, which has been the only way I have ever really learned anything.

Factor this:

“One additional thing on ULK... the fact that Intel is ramping 45nm with a more conventional ILD is another example of Intel being able to extend things further in manufacturing through better integrated performance. (In other words new != better). That Intel is not doing ULK on the order of IBM, speaks to Intel's overall backend capabilities.”


AND-----------------------:

“This is much like immersion litho - while cool and it makes it sound like AMD is more advanced for using it, those in the know realize that it is FAR better to extend known technologies and introduce new things only when they are absolutely needed or yield a huge performance or cost benefit. As immersion litho will simply enable AMD to achieve the same feature size as Intel does with dry litho and is at best cost neutral with a dry litho double pass process (many think immersion at least initially is MORE expensive) - makes folks who work in the biz think 'why is moving to immersion litho on 45nm a good thing again?'"

"While ULK (or in generally the bulk dielectric) gets the press, the key on the C part of the RC delay is the effective capacitance which includes the barrier layers used (which is needed to enable the etching of lines/contacts for the metallization process on each layer). If you use an exotic low K, but it needs an etch stop layer which is either a significantly higher K film or is needed to be thicker, then the bulk ILD ULK really doesn't buy you anything. If you want to compare ILD capabilities, one should compare effective K of the entire ILD stack (not sure if this info is published generally speaking”

Furthermore-----------------------------:

“Design - the density of lines, length, layer to layer separation all effect RC delay. You can add more metal layers (like AMD) to lower the density of metal lines and prevent line to line or layer to layer capacitance issues. This is an area that falls into the "restrictive design rules" philosophy. If you have a known process capability you can give the designers very clear limits on what they can and cannot do. Or you can do a design with no (or fewer) constraints and move to more exotic materials or add extra metal layers to make it work.”


There is no book on the planet where you could get this. All you need to do is read, research, reread, define terms, and try to understand what the hell he is talking about!

Sputtering, ILD, immersion, patterning, annealing, etching (I knew this one I make my own circuit boards), Dry Litho, and last week, it was Isub leakage!

My reward, you ask? I got a “not bad” from GURU for telling Charlie D. publicly he was full of shit! Furthermore, getting a “not bad” from GURU brings me one step above protozoan in the relative scale of things. And, that’s saying something!

Beside, it’s more fun this way, and perhaps others will pick up a thing two. I think it’s better for this wonderful site, on the whole.

That said, GURU has sent me on a mission: I’m on to gate leakage!

PS Tell Big Paulie I’m waiting for my dividend check. There’s a QX9770/ASUS Rampage Extreme X48 in my future.

SPARKS

Ho Ho said...

"Overall L3 amount is smaller for the duals"

It is? I've never seen anything about dualcore K10's with less than 2M of L3. It would be kind of pointless to have any less than that.

Anonymous said...

'PS Tell Big Paulie I’m waiting for my dividend check. There’s a QX9770/ASUS Rampage Extreme X48 in my future.'

You're more likely to get a capital gains check - the stock should run up some more in advance of earnings announcement tomorrow evening; though I wouldn't be surprised even if Intel meets or exceeds earnings to see the stock take a dip on Wednesday.

Not sure I would bother with the X48 right now though, it is likely to go through some growing pains early on... does it offer that much more than X35 or X38 boards? (I know those don't officially support 1600 FSB, but I imagine they will?)

With Nehalem coming down the pipe, I'm not sure the X48 offers more in terms of future upgradability as Nehalem will mean a new socket. Anyone have thoughts on this?

And thanks for the kind words. If you can understand Isub, gate leakage is far easier / more intuitive.

InTheKnow said...

With Nehalem coming down the pipe, I'm not sure the X48 offers more in terms of future upgradability as Nehalem will mean a new socket. Anyone have thoughts on this?

Sockets aside, I can't see the X48 boards being upgradable to Nehalem. Nehalem has an on-board IMC, which means a totally different chipset will be needed to support the chip.

Though this gets into the whole question about what Intel meant about Nehalem being "modular."

Depending on the degree of modularity, we may see desktop Nehalem continuing to use the FSB. Despite what the AMD faithful may say to the contrary, HT doesn't really offer that much on a single socket system.

If there will be FSB compatible Nehalem chips, I would think Intel could pin it to use the existing socket and use an X48 board.

Anonymous said...

EPS 0.38 vs 0.40 expected
Revenue 10.7 vs 10.8Bil expected
(last year = 0.26 EPS and 9.7Bil Rev)

It'll be interesting to see what AMD reports later this week.

Anonymous said...

gross margins were 58.1% (so much for the price war)

SPARKS said...

EPS 0.38 vs 0.40 expected
Revenue 10.7 vs 10.8Bil expected
(last year = 0.26 EPS and 9.7Bil Rev)

Ya beat me to it. The fly in the ointment, with the anal-ist, is INTC didn’t quite “meet expectations” 2 cents a share, and 10 million, oooh what a hit! (Sarcasm implied). 10 million is probably INTC’s yearly expenditures on toilet paper and feminine products, worldwide. I’ll take the 38 cents on the quarter thank you very much.

Orthogonal, keep up the good work and keep that nose to the chipsets.

“Not sure I would bother with the X48 right now though, it is likely to go through some growing pains early on... does it offer that much more than X35 or X38 boards? (I know those don't officially support 1600 FSB, but I imagine they will?)”

Yeah, sure, growing pains, my ass! I assume we are speaking about the 1600 MHz “crosstalk, 6 layer board issue”? INTC laid down on the release of X48 so its partners could unload current X38 inventories. Here is what X-bit labs said about these “issues”!

“And although Intel has found an excuse – an alleged problem in the upcoming processors caused by EMI in 1333MHz front side bus when these CPUs are used in hypothetical mainboards with 4-layer PCB design – it doesn’t sound convincing at all.”

http://www.xbitlabs.com/articles/cpu/display/intel-wolfdale.html

Yeah ok, turn my head and cough. No, I WANT THAT NATIVE 1600FSB DAMN IT. As far as Nehalem is concerned, it’s a non issue as far as I’m concerned. If QX9770 is EOL’d, I’ll keep the last of the great FSB chips for my fabulous collection x86 chips INVENTED by Intel Corporation.

GURU, the Isub, Igate is a bit more complicated than you suggest, from where I sit they are very much interrelated.

“For (Tox)> 20 Å, is typically very small in comparison to other forms of leakage current, specifically subthreshold
leakage (Isub) which arises due to the partial formation of a conducting channel even at Vgs=0v . In recent generations, (Isub)
has been seen to rise by a factor of 3 to 5x per generation under
normal scaling theory. On the other hand, (Tox) is 30% thinner in
each new process technology and for an initial (Tox) of 20 , this
results in a 1000 x rise in (Igate) in a subsequent process with (Tox) of 14 Å (it will be somewhat smaller due to a reduction).

It is clear that (Igate) either will, or in some cases already has,
caught up to (Isub) in magnitude.”

http://www.gigascale.org/pubs/528/Lee_TVLSI_Feb04_published.pdf


1000 times!!!

It seems even though a couple of IBM guys wrote this paper in 2004, AMD and IBM together couldn’t get a handle on it. What I am trying to grasp is the effect one has on the other with electron tunneling thing going on. (I suspect this is what you were referring to with “additional metal layers” associated with costs)

It sounds to me like a runaway thermal effect in one of my Class A homebrew bipolar transistor amps gone badly. Very fugley.

SPARKS

Giant said...

No, I WANT THAT NATIVE 1600FSB DAMN IT.

Does it really matter sparks? With an unlocked multiplier on the QX6950 you can easily set a 1600MHz FSB, and set the clockspeed in 200MHz increments with the 1/2 multipliers.

At this stage though, with the mainstream Yorkfields coming in March I'm thinking that I'll just keep this system as-is until Nehalem is launched later this year. Buying a new processor with a six month lifespan before Nehalem doesn't make sense to me.

Intel's earnings were great. Very strong YoY growth. $2.3bn in profit must make Hector go green with envy! I wonder what will happen to Sharikou's BK prediction because of this?!

Anonymous said...

"No, I WANT THAT NATIVE 1600FSB DAMN IT."

Ah, a question of manhood, I see. :}

SPARKS said...

Giant! Et tu Brute? Here I thought you were my overclocking, peddle to the metal, balls to wall, clock till ya rock, buddy? I’m shocked and appalled! This is not merely a mater of dialing in the extra 266 MHz and saying, I’ve got the same thing, performance wise.

God forbid!

IT AIN’T. This is a factory authorized, 1600FSB 45nM gorilla, from the most sophisticated process/design facility in the world. This is a piece of CPU history. The High Priests at Chipzilla have given this Archangel their blessing to go out into the world and destroy the demon copy cats with sanctimonious, religious fervor! This is the one that was designed to take on, “The “B” Who Not Shall Be Named”, even if the “Scrappy Little Company” got it right.

Perhaps it will be the last of its breed, sans IMC. It’s the changing of the guard, the end of an era, or the last of the Mohegans, of sorts. They built a 4.5 Billion dollar factory to make these little gems, and I want apiece of rock, baby! Mine, mine, mine,------!

I’ve had my eyes on this little sweetie for six months now. They could stand me up at the gates of HELL and I won’t back down, not now!

I don’t see any AMD posters or bill boards walking down Park Ave. now! Hey, eat this:

QX9770, so good they had to pull the reigns in on it.

Hey as far as the manly thing goes, take 1 Extenze, two Viagra’s, 1 QX9770, and give the old lady the ride of her life!!!


HOO YA!

SPARKS

sparks said...

Need my ass fucked good!