9.10.2007

Time Of Death: 0:00 am September 10 2007

AMD’s new micro-architecture was officially launched today and at no surprise to anyone who contributes to this blog, Barcelona is dead on arrival. Doubters like ourselves were told to wait for this day. Sept 10, 2007 was supposed to be the day AMD takes back the performance crown to the rejoicing of its followers. But yet again, AMD disappoints. The promise of a 40% performance lead at the beginning of the year was cunningly and gradually reduced to a trivial performance-per-watt advantage. An advantage that current K8’s probably already had but nonetheless insignificant to prevent AMD’s market share erosion.

To AMD's credit, the improved IPC that Barcelona brings with it is quite noticeable. Whereas in the past the K8’s were severely lagging both in clock speed and in IPC. But with Barcelona the gap narrows down to raw clock speed. Like we mentioned several months ago, GHz is once again King and AMD’s clock frequency problems aren’t quite easy to overcome. Anyone speculating that AMD can ramp its 65nm SOI to 3GHz by Q1’08 is only preparing for another public humiliation. For a number of reasons; Barcelona’s already high thermal dissipation at 2GHz, its poor 65nm SOI process and the very large die, all create an insurmountable barrier that AMD can never overcome. You should notice how Barcelona is debuting with a very low clock frequency with an already high 2.6Ghz original power draw.

From the TechReport:

Note: Sample benchmark from TechReport and may not be representative of the entire comparison.

“Nonetheless, AMD now faces some harsh realities. For one, it is not going to capture the overall performance lead from Intel soon, not even in "Q4," which is when higher-clocked parts like the Opteron 2360 SE are expected to arrive… On top of that, Intel is preparing new 45nm "Harpertown" Xeons for launch some time soon, complete with a 6MB L2 cache, 1.6GHz front-side bus, clock speeds over 3GHz, and expected improvements in per-clock performance and power efficiency. These new Xeons could make life difficult for Barcelona… this CPU architecture may not translate well to the desktop, where it has to compete with a Core 2 processor freed from the power and memory latency penalties of FB-DIMMs…”

From Anandtech:
“When you are looking for the highest performance however, Intel has still a solid advantage with it's 3 GHz Xeon x5365”

Note: Sample benchmark from Anandtech and may not be representative of the entire comparison.

Anyone thinking this is a good start for K10 is fooling themselves. This is a terrible start for any new product, never mind one that is desperately needed to be better than the competition. When Core2 came out and trounced everything AMD had, even Hector Ruiz was forced to admit that a new generation processor is always expected to "leap-frog" the competition. Clearly things are different this time around. Barcelona's problems and delays when combined with Core2's massive performance improvements over previous generations created a gap too wide for AMD close. For the first time in several processor iterations between Intel and AMD, the latter's new processor falls short. While AMD will be stuck with an already beaten K10 design for the next 3-4 years, in a few months Intel will move to 45nm that will allow it to clock even higher, reduce the cost even further while drawing less power. Expect the gap on any meaningful metric to continue to increase as AMD's K10 is simply not good enough.

78 comments:

Anonymous said...

I think you're mistaken - Scientia just proclaimed "K10 - A good start"

A few good excerpts:

"K10 has been essentially finished since mid 2006 so the major team would be working on Bulldozer while an upgrade team handles both the launch and the later Shanghai version."

"There is no way to know exactly what went on at Intel but given the fact that we know roughly what Intel knew we can make some reasonable guesses"

Reasonable != Scientia

"I'm sure that AMD felt that their dual core design was enough to tide them over until K10 was released and I'm certain they didn't foresee Intel's use of MCM to create a quad core."

They didn't foresee an MCM!?!? Hello, PENTIUM PRO anyone? P4 dual cores, anyone? If AMD couldn't foresee an MCM solution using Core2, I'm wondering if they can foresee whether or not the sun will come up tomorrow.

This AMD excuse mongering is really destroying any credibility that Scientia had built up in the past.

It's rather sad - I wonder if he invests in the stock market, because his linear logic style would get him smoked! Let's see this is how things worked awhile ago, so we can use that to predict the future. Isn't that how things work? Forget fundamentals, environemental factors, etc.. just look 2 years ago Intel went up 10% between Jun and Jul, therefore next June I should buy it and sell it in Jul!

While folks can learn from the past, it is ignorant to blindly apply that to predict the future! Nor are empirical observations fitted to a preformed conclusion a way to prove that conclusion. Scientia lacks a basic understanding of the fundamentals and as such he simply fits the empirical observations to what he thinks they should be - look no further than his explanation of how the design teams worked and were formed, retasked, etc..

Anonymous said...

Ha - Ruiz did an interview with CNBC, and continued to reiterate this launch as the most important of 2007!

One would think with such a launch there would be a slew of extremely detailed reviews to showcase the superiority of this revolutionary new product. You know much in the vein of AMD proclaiming that this would be 40% better than Intel's BEST part at launch.

I guess Hector failed to mention to the press that as part of the "Asset lit" strategy, AMD will no longer be doing benchmarks (Hey it's expensive to do build these computers and then buy all that SW and test them). They also will attempt to cut costs going forward by not sending out any samples for review (or sending them only to "pre-approved" reviewers)

The scary thing, is that if they had delayed this launch to the new stepping (~3 months or so), they could have had more reasonable parts, would not have had to price them so low, and would have been able to actual provide samples to the press and actually have the product benchmarked prior to asking people to buy it on faith.

I wonder how much revenue AMD will take in over the next 3 months on Barcelona and whether it will be worth the negative momentum these low end parts will be building up?

As usual, AMD's parts are synonymous with "value" (read cheap), efficient, etc... The adjectives nowhere to be found? HIGH PERFORMANCE

They had one site review a 2.5GHz chip -knowing full well the best they will do at launch is 2.0GHz. Why? Is it normal to provide a part for review at launch that will not be available for at 3-6months. When Intel launched Core2, were they sending parts clocked higher?

It will be rather interesting to see how the press covers this launch over the next few days and whether AMD just gets a pass as the lovable underdog...

Anonymous said...

For those saying - the high speed parts are coming the high speed parts are coming!

Anandtech's review of a 2.5GHz ES was running at 1.52Volts! Certainly sure to be an overclocker's dream for Phenom customers no? I hear running at high voltages is generally an indication of a lot of headroom, no?

Well there's always the B3 stepping? B4 anyone? B4 = BE-FORE CHRISTMAS '08

Roborat, Ph.D said...

i find it laughable that anyone would assume that Intel's 45nm will have bad yields at launch when clearly it has been demoing the part at full speeds 1 year before launch.
45nm was an easy transition for Intel using mostly similar tools for the transition. 45nm is dying to get out of the Fab if not for Intel trying to maximize 65nm ROI.

As opposed to Barcelona reaching mature yields? 6 months late and 600Mhz underclocked. I can't possibly imagine AMD ramping 45nm "middle" of 2008 when they can't even fix 65nm. Wishful thinking for anyone wanting to believe a company who's hasn't delivered anything it originally promised for over a year now.

InTheKnow said...

Roborat said...
45nm is dying to get out of the Fab if not for Intel trying to maximize 65nm ROI.

I think that is a bit optimistic. Right now Intel only has one fab producing 45nm (D1D) and it is a smaller volume fab. I think Intel is looking for F32 to have volume production in F32 in order to be able to properly supply the market before releasing it.

65nm is still going to be supplying the bulk of the desktop and mobile markets anyway, so the ROI is there in any case.

sparks said...

Did anyone notice the test setups at Anandtech were on nVidia chipsets???

WHY???

Whoops!

SPARKS

13ringinheat said...

Hahahha someone predicted that AMD will release barcelona with some stupid benchmark/segment to show how good its processors are and sure enough here comes AMD with its retarded ACP......pathetic.....

AMD powered by barcelona......supported and run by retards

SPARKS said...

Wait it gets better. Anand was very kind with the benchmarks. The comparisons were made with the E5345 at a $455 price point; as opposed to outright price is no object, performance comparison. (First value gaming, now value servers.)Hell, Anand didn’t even include the E5355 and E5365 in the tests! Now you know why Barcelona was priced so low. It had to be cheaper than the E5345, and it still took a shellacking in many benchmarks.

There’s your comparison, performance per watt, price per watt, and mixed reviews.

I can hear them spin now, ‘you see, we beat Clovertown!’ Yeah sure, the little guys, not the big brothers.

5.4 BILLON FOR ATI AND THEY ARE RUNNING THEM ON NVIDIA CHIPSETS! WTF IS UP WITH THAT!

The bottom line here is why anyone should buy a Opteron platform 2350, to upgrade later when faster chips become available, when you could buy a E5355 or E5365 now, skip the upgrade, and the additional cost(and downtime) of another processor upgrade? (This is not to mention another major Intel upgrade option in November) And, this is all contingent on Barcelona scaling to 3 GHz, not with those thermals at 2 GHz, not at 65 nm, and not with SOI.

Over one year of bullshit and spin for this? Now you KNOW why top exec’s bailed!

WE HAVE BEEN RIGHT ALL ALONG. This entire blog IS PROOF.

SPARKS

Anonymous said...

"45nm was an easy transition for Intel using mostly similar tools for the transition. 45nm is dying to get out of the Fab if not for Intel trying to maximize 65nm ROI."

45nm, while on track and exceuted well, is by no means an easy transition. The introduction of High K/metal gate introduces several brand new process steps and fab tooling - specifically atomic layer deposition. It introduces new failure modes in the gate oxide which have to be tested (and were not a concern with conventional SiO2), as well as new test structures required.

I have had the pleasure to work on some of these tools, they are very finicky, have slow throughputs and take quite a bit of work to get defect levels low. Additionally some of the precursors used in these processes are especially difficult to work with as they are not common, difficult to purify and not easy to deliver to the tool in high volume manufacturing.

The fact that Intel is on schedule (actually they are ahead of schedule as 65nm product was first out in Jan'06 and it looks like 45nm will be sooner than Jan08), is no minor testament to their development and manufacturing muscle.

If you'll notice despite IBM CLAIMING to have a high K/metal gate solution, AMD has said best case the end of 45nm node or 32nm - I'm quite certain if they tried to implement at onset of 45nm AMD's line would grind to a halt. They will say it is not needed and that quite frankly is CRAP - if it was needed AMD would have no chance of implementing anyway so that's a convenient excuse (especially since AMD is claiming they only expect to get a 20% benefit from 65nm to 45nm which is pretty low for a node transition)

Anonymous said...

"Hahahha someone predicted that AMD will release barcelona with some stupid benchmark/segment to show how good its processors are and sure enough here comes AMD with its retarded ACP......pathetic....."

Good to see someone reads my posts!

Though rather than pat myself on the back, I must admit this prediction was about as obvious as me predicting that I believe the sun will rise in the East tomorrow.

Anonymous said...

Kind of funny no-one has really taken notice that Anand's 2.5GHz engineering sample was running at the ridiculous voltage of 1.52V!

Improved stepping or essentially overclocked? Voltage should be lower than 1.35V (and potentially as low as 1.15V) for the 65nm process no?)

BTW - InTheKnow - while D1d is perecived to be a relatively small fab, it's volume is actually much larger than people think!

If Intel is running in the neighborhood of 2500-3500 WSPW (which is probably conservative), this equates to roughly 11K-16K wafer starts per month...

..or to put things in perspective not that much smaller then AMD's ENTIRE 65nm PRODUCTION LINE RIGHT NOW (~20K WSPM)...factor in die size from the 45nm node and D1d by year end might be able to produce more 45nm chips than AMD's F36 65nm chips!

...this alway makes me laugh when people like Dementia, say well D1d is only producing "small volumes". I guess when it is 1/2 to 2/3 of AMD's current F36 production should be considered peanuts when you think about it...

Axel said...

Another post that Scientia is likely to delete/edit, saved here for posterity.

Scientia

Not really. I looked at the Tech Reports review.

I'm pretty sure you didn't look at the same review that I did, since you still stubbornly hold to the mistaken opinion that K10 has a general 17% IPC lead over Clovertown. Let's look at those review results a bit closer:

The numbers below represent how much higher/lower K10's IPC is compared with Clovertown GHz on the 2.0 GHz test systems.

SPECjbb: 2.1% higher
Valve VRAD: 13.1% lower
Cinebench sngl: 16.3% lower
Cinebench mult: 10.7% lower
POVRay chess: 3.8% higher
POVRay bench: equal
MyriMatch 1 th: 9.1% lower
MyriMatch 8 th: 1.8% higher
STARS 1 th: 29.2% lower
STARS 8 th: 13.3% lower
Folding avg: 3.0% higher
Panorama Fact: 12.9% lower
picCOLOR: 20.0% lower
WME encoding: 6.3% lower
Sandra Mult Int:47.8% lower
Sandra Mult FP: 11.6% lower

Now how does this data even remotely support your position that K10 generally has 17% more IPC than Kentsfield/Clovertown? If I take the crude liberty of averaging those numbers above, I find that K10 is in fact generally 14.4% slower than Clovertown per clock.

So it looks like you've made the mistake of taking Anandtech's server oriented benchmarks and extending that IPC relationship to the enterprise & desktop spaces. I'm stunned at your naivete. The enterprise trend is covered by Tech Report's benches above which clearly show that K10 has a significant per clock deficit against Clovertown in that space.

For the desktop we have Anandtech's preview using registered DDR2-667 memory, showing a 10%-15% IPC gain over K8, which is some 10-15% short of Kentsfield. Think what you want, but faster unbuffered memory is unlikely to net more than a 5-10% gain in IPC. The conclusion is clear: K10 is unlikely to even catch up with Kentsfield on the desktop, certainly not in games where Kentsfield's lead over K8 is huge. Penryn will extend this desktop lead further and add SSE4 to the equation, completely destroying the larger die K10 in the desktop space.

Giant said...

South Korea finds that Intel has done nothing serious enough to warrant sanctions:

All they did was send Intel a "statement of objection".

http://www.smh.com.au/news/Technology/South-Korean-antitrust-regulator-completes-Intel-probe/2007/09/11/1189276694226.html

AMD's lawsuit is without any merit whatsoever and will be thrown out.

Anonymous said...

wat a dumass that brent rehmel

Axel said...

This is by far the most bafflingly disappointing launch of a new generation of CPUs ever. A grand total of about four reviews? No buzz on web sites, fierce debates in forums, etc? I was looking forward to several days of post-launch excitement, reading tons of articles on dozens of sites, and just wished for K10 to put up a huge fight despite all indications this year to the contrary:
- The covertly obtained Cinebench & POVRay benches.
- AMD's refusal to publically exhibit K10 performance
- Three high level executive resignations
- Hector's hints that K10 wouldn't make the splash that K8 did.

It seems as if both Intel & AMD advocates have been stunned into silence by the revelation that the emperor really had no clothes after all. It truly is too little too late, even if the clocks come up. Though the memory subsystem architecture is innovative and efficient, AMD simply didn't do enough to the actual core to greatly improve IPC over K8. K10 is essentially the K8 motor with new heads & cam, when what AMD really needed was to retire the old motor and replace it with a new big block or at least outfit it with a supercharger.

AMD's only hope now is that the B2 stepping not only brings the clocks up, but has significant IPC gains as well over B1. However, as we know, core steppings rarely increase IPC at all but usually only fix errata and optimize transistors & thermals.

Anonymous said...

i find it laughable that anyone would assume that Intel's 45nm will have bad yields at launch when clearly it has been demoing the part at full speeds 1 year before launch.

Well Intel demoed one Conroe processor at 2.93Ghz almost 2 years ago….. Guess what? Intel is at 3.0Ghz today!!!! An 70Mhz clock increase!!! Amazing!!!
But forget this, Intel is superb and AMD sucks it’s easier to say.


If Intel is running in the neighborhood of 2500-3500 WSPW (which is probably conservative), this equates to roughly 11K-16K wafer starts per month...

..or to put things in perspective not that much smaller then AMD's ENTIRE 65nm PRODUCTION LINE RIGHT NOW (~20K WSPM)...factor in die size from the 45nm node and D1d by year end might be able to produce more 45nm chips than AMD's F36 65nm chips!


Read the news, Toms, where you want, AMD have been increasing its market share, meaning its products are selling! That just leaves your lovely company with more inventories that can’t sell…
Too bad AMD filled a lawsuit complaint against Intel, and can’t no longer do more illegal tactics to get rid of it. Poor Intel… still having a hard time trying to sell those 70º Q6600 revision B3 processors that nobody wants…


Axel you noob, trying to compare Server processor performance running desktop applications VS Intel desktop processor. Want to try Doom3 on one Xeon FBDIMM processor VS a 3.2Ghz Athlon K8? Or even one Xeon VS Core 2?


Again to the noob, do you would like Gamespot for example to review the Opteron processor? That would be nice like one Sports site talking of Politics, that would be super doper!!!

Anonymous said...

"This is by far the most bafflingly disappointing launch of a new generation of CPUs ever."

I think you use the word launch a bit too liberlally. Where can one buy a server now that Barcelona is "launched".... Remember AMD doesn't do soft launches.

Even Fudzilla is wondering where the availability is.

This is more like - 'crap we said launch before end of summer...ok let's get out the powerpoint foils, screw the benchmarks, screw the product availability and hey let's make up a new power consumption metric to buy us some time while folks wonder what the hell it means.'

It'll be curious to see Dementia call this is "real launch" (you know because Penryn's launch won't be real due to limited availability until Q1'08)

Anonymous said...

"Well Intel demoed one Conroe processor at 2.93Ghz almost 2 years ago….. Guess what? Intel is at 3.0Ghz today!!!! An 70Mhz clock increase!!! Amazing!!!
But forget this, Intel is superb and AMD sucks it’s easier to say."

Hey idiot - please let me know how Intel managed to get quad cores in the same power envelop without making any improvements. When you improve with future steppings you can either jack up the speed or the power... Intel has doubled the # of cores in the same power envelop!

And please learn the difference between binsplit and yield... just because you don't get higher speed bins doesn't mean yields are bad.

If you do think this, you may want to ask yourself what AMD's 65nm yields are right now as their K8's are 400-600MHz BELOW 90nm. In your vastly superior comprehension of yield what does that say about AMD's yields? (in truth it says nothing, just like your dumb point on Intel's clocks)

You need to stop relying on Scientia's blog for your learning about process technology.

"Read the news, Toms, where you want, AMD have been increasing its market share, meaning its products are selling!"

US Retail desktop/mobile share! WOW! That's almost <10% of overall x86 CPU market share. I stand corrected! For 1 month! Don't worry Q3 #'s will be out soon - sounds like AMD has taken massive amounts of market share back based on Intel's forecast yesterday.

Scientia, is that you? The complete incorrect use of facts to support a preformed argument seems familiar. Or is it one of you underlings?

Funny with K10 all "launched" and everything you would thing the fanboys would be out in droves talking about all those benchmarks demonstrating its superiority...oh there are few to no benchmarks? ANd it isn't 40% better? That can't be right...

Intel must have paid off EVERY REVIEW SITE not to review this chip - damn monopoly tactics! AMD should sue them for suppressing all of those wonderful benchmarks! (At least then they'll have an even outside chance of making some money!)

Giant said...

"Well Intel demoed one Conroe processor at 2.93Ghz almost 2 years ago….. Guess what? Intel is at 3.0Ghz today!!!! An 70Mhz clock increase!!! Amazing!!!

As the other Anonymous pointed out, they've gone to quad core as well. Going from E6600 to Q6600 (both 2.4ghz) has decreased my video encoding times by 70%. That's right. A 70% performance improvement. Same motherboard, memory, video card etc.

Also, where did that stupid 70C remark come from? No one cares the maximum amount of heat the CPU is rated to handle. My Q6600 is B3 revision from right after the price cut to 535 from earlier in the year. At stock speeds it hits 51C on a full load across all four cores. Even overclocked to 3Ghz it's still well under 70C. (Hits ~62C)

Finally I've decided to look at the Barcelona launch from your perspective. Intel increased clockspeeds 70mhz. AMD dropped them 1.2Ghz! That's a decrease of 37%!

As Anonymous also kindly pointed out, why would Intel increase it's profit and revenue outlook for this quarter if AMD was taking so much market share away?

Wouldn't they be losing revenue and profit if this was the case?

Anonymous said...

Hey idiot - please let me know how Intel managed to get quad cores in the same power envelop without making any improvements. When you improve with future steppings you can either jack up the speed or the power... Intel has doubled the # of cores in the same power envelop!

If for you 65W == 130W you are right!
The Intel quad cores CPUs consume the same of the Intel dual cores CPUs especially at idle! Amazing!!!


Giant,
your post is quite correct! Except the end part, maybe Intel revenue comes from higher profits? Selling “fewer” CPUs at higher prices make more profits?

SPARKS said...

"Well Intel demoed one Conroe processor at 2.93Ghz almost 2 years ago….. Guess what? Intel is at 3.0Ghz today!!!! An 70Mhz clock increase!!! Amazing!!!"

Ah, yeah, this is true, to a point.

But then I think you are forgeting one thing, XE's. You see, I doubt you've ever owned one. If you did, you would come to realize that C2D's have PLENTY of headroom. You just go into the bios, step up the multipler, and viola, 3.8 gig, 24-7, no problemo! HOO YA!

Thermals? Power? Who gives a FF. Feed it lotsa juice. (Nothing less than 1kw just for fun) Hose it down with a little water (Black Ice Triple prefered) and it's playtime, bigtime!

This is the kind of headroom Wrector Ruins can only DREAM about. "AMAZING!"

THERE IS NOTHING LIKE A UNLOCKED EXTREME EDITION.

NOTHING.

SPARKS

SPARKS said...

Oh yeah, one more thing, DON'T buy one! They're like CRACK! Ya can't get enough of them and you never settle for less again!

DA BOMB!

SPARKS

13ringinheat said...

Anonymous idiot said: Well Intel demoed one Conroe processor at 2.93Ghz almost 2 years ago….. Guess what? Intel is at 3.0Ghz today!!!! An 70Mhz clock increase!!! Amazing!!!
But forget this, Intel is superb and AMD sucks it’s easier to say.

They actually demoed a 2.66Ghz conroe and then released a 2.93ghz part upon release..........

http://www.anandtech.com/tradeshows/showdoc.aspx?i=2713

AMD powered by barcelona......supported by retards

SPARKS said...

Lets put this market share and financials to rest, now.

http://news.moneycentral.msn.com/ticker/article.aspx?Feed=AP&Date=20070910&ID=7444098&Symbol=AMD

CASE CLOSED

SPARKS

Andy said...

Why would Intel up their clock speeds when their opposition has given them no reason to?
No point forcing yourself to lower prices.

Oh wait, that's what going to happen to AMD though when all their old 90nm parts aren't selling because all people want is Barcey!

SPARKS said...

CHA CHING!

http://eastbay.bizjournals.com/eastbay/stories/
2007/09/10/daily2.html?from_msn_money=1

SPARKS

Andy said...

I think Intel are lying. Well they have to be. They are going to BK in Q4.

Anonymous said...

Sparks - I think Intel's news is also good news for AMD as well - it more than likely means that the overall market grew more than expected, not retaking major market share.

Still rather impressive though - the new low end of the revenue range is higher than the previous middle of the range.

Of course AMD will still likely lose money...just less of it. (My guess is ~200-250Mil)

InTheKnow said...

BTW - InTheKnow - while D1d is perecived to be a relatively small fab, it's volume is actually much larger than people think!

No, it is not. I was only saying that relative to volume that Intel needs to support their launch they need F32 on line, or at least with risk Si in line.

Obviously, AMD with their much smaller volume share doesn't need to have as much capacity.

InTheKnow said...

A small fab that is. :)

Anonymous said...

what kinda dumbass would think that 2007 would be a great year for AMD after Core 2 and that K10 would rock when everything else suggested otherwise?

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lol

SPARKS said...

“Sparks - I think Intel's news is also good news for AMD as well - it more than likely means that the overall market grew more than expected, not retaking major market share.”

Quite right, 200 to 300 million loss and increased market share, no doubt. It’s like a dog chasing its own ass. However, one must also factor that they are not covering the developmental costs of the seriously delayed Barcelona product line. Further, they will never see the expected revenue associated with a new launch. With the limited (and specialized) market they’re targeting, it will not be nearly enough to stop the losses. CAPX for R+D is probably cut to the bone.

Maybe, from their perspective, 200 million losses seem great after 3 consecutive half billion dollar losses. Perhaps Wall street will think so, too.

As we all know, maintaining market share has not helped AMD make money. Exacerbated by a very late desktop product, they will miss, yet, another holiday season. Even if Pheromones are launched at 2.5 GHz, I doubt it would be priced high/competitive enough to stem more losses, even if they can crank out a substantial number of chips.

Unfortunately for AMD, great chip or not, the entire line is 6 to 9 months behind. Intel has another price cut scheduled and they will be ramping 45nm, as they have recently announced the end of the 65nm product line. C2D will become more attractive as the holidays approach, and Intel can bargain out more inventory as Penryn starts to ramp. (Obviously, as you say “the new low end of the revenue range”) If and when Nehalem launches for the ‘server set’, it’s game over.

I know it’s upsetting to the AMD boys, but with this much of a lead, Intel can pee on AMD’s parade any time they want, 1600 FSB’s, higher clocks, more dies per wafer, lower prices, screaming 1800 DDR3, 45nm, and more Fabs to do it. (Arizona D1D opens for business in 6 weeks, nice timing wouldn’t you say?)

Therefore, the question begs, where does AMD go from here and now, and with what money, even if they (miraculously) break even? What new architecture will they have even if this thing does ramp to 3.0 or better? This product cycle, from a revenue perspective, will not be a two or three year deal, no way. Those days are over. At this juncture, even a 50 million dollar loss is going to hurt. Frankly, I really don’t see an end to it.

As for Intel, holy cow, 10 Billion a quarter, and 52 percent margins, man, we haven’t seen that in a while.

I am compelled to say, however, I truly feel for those guys in the white suits at AMD. They are working their asses off, with limited resources, to save the company, despite reckless managements’ tragic, monumental mistakes. God help/bless them all.

SPARKS

Anonymous said...

"Quite right, 200 to 300 million loss and increased market share, no doubt. It’s like a dog chasing its own ass."

Agreed...but overall market growth at this point will probably help AMD more than Intel (unless AMD loses share). If they just raised ASP's a bit and let market growth compensate for share loss they would be selling near the same amount of chips at a higher price... that would allow them to get in the black and start to grow capacity again. It's not like Intel would also not like to raise their ASP's a bit as well for their stockholders, plus they can't afford to completely wipe out AMD for strategic reasons.

AMD is like that guy in Risk who attacks everyone in the 3rd or 4th turn of the game, takes a huge amount of territory and is spread paper thin but feels real great about owning so much territory. This wakes everyone else up and all the short term gains are quickly wiped out because he did not build up in a sustainable fashion. That person then whines 'everyone's ganging up on me, it's not fair' (sound like a certain company saying, Intel's a monopoly that's not fair?). And then that person either gets wiped out of the game, or crippled to the point where they are no longer a viable threat (I think Intel's strategy is the latter)

BTW - 200Mil in losses would be perceived as a HUGE WIN for AMD and I would expect the stock price would jump. I'm not saying 200Mil loss is a good thing but the expectations right now are very low. The reason for this is Q4 market will be better overall and 200mil loss this quarter would put them on track to get even in Q4 which I think Wall St would consider the best case scenario.

Of course it depends how AMD achieves their loss figure - if it is do to one time events (tax break, equipment sales, etc..) then Wall St will look harder at it, but if it is through CPU revenue growth...

As for Phenoms - they will do well REGARGLESS of performance (early on). They are enoough of the "support the underdog", "Intel is evil" and "I only buy the more elegant design (who cars about performance)" folks that wil buy whatever limited supply AMD will be able to provide in Q4. The problem will be in H1'08 if the desktop performance is not competitive.

If I were AMD, I would not do the foolish server launch of just shipping whatever bin they can get out the door. They clearly need to wait until a high bin part is ready and milk those early adopters/fanboys for all they can. If not those folks will buuy the cheap parts and not bother when the more expensive ones come around.

Even if it means missing the holiday season! (With expected volumes it;s not like this is going to do much to their Q4 bottom line anyway!)

AMD needs to learn how to run their company like a business not as a bunch of engineers in search of the best or most elegant (our quad core is native, not "glued" together) product or an egomaniac who can't settle for being a profitable #2 CPU company.

Anonymous said...

"was only saying that relative to volume that Intel needs to support their launch they need F32 on line, or at least with risk Si in line. "

D1d at full bore could probably support >10-15% of the overall market. This would be fine for the first quarter or two of a launch (especially if the launch is focused on server) Of course it is still doing a sizable chunk of 65nm (which will be scaling down) and will be picking up 32nm development line (already started), so it is not sufficient.

It's just kind of funny when Scientia thinks development fab - it must be small. When built out D1d may have a higher overall capacity than AMD's F36 (in terms of wafer outs). At half capacity and a technology node ahead it is probably nearly equivalent. What is amusing is something this size is only capable of a paper launch, while Scientia talks about AMD 45nm in Q2/Q3 which will be a small portion of F36 (which would be DWARFED by D1d alone). So scientia talks about Q1 as the "real" 45nm Intel production, while AMD's "real 45nm production will be Q2/Q3 (only six months behind!) and at that time AMD's 45nm will be an even smaller capacity then Intel's Q4'07 45nm tiny launch...

Moral of the story - Scientia knows NOTHING about manufacturing, capacity, and process technology and simple regurgitates facts out on the web and is therefore unable to understand when he is comparing apples to oranges... if you think otherwise, ask him how ZRAM is (not) working out! If he actually had done some reading on the technology as opposed to just quoting AMD press releases on that subject perhaps it would not have been on some of his roadmap blogs....

Anonymous said...

Sorry forgot the supporting statements for the previous comment:
"We also know that Intel will eventually use SOI as AMD has been doing for years now."

(Hmmm.. seem to recall an article that AMD is debating on whether to go back to bulk Si for 32nm....perhapa someone doesn't understand the issue around SOI - especially with linewidth scaling?)

"AMD has at least two other possibilities to compete with Intel's 45nm in 2008. These include the possibility of using TTRAM or Z-RAM for cache."

So anyone want to bet on whether AMD after releasing K10 in Q4, decides to completely change it's cache structure on this design. Scientia read - SOI, high density and said unique competitive advantage to Intel. Had he read details he would have see slower cache, not proven in production and several alternatives (like 1T-1C cells) that appear to be much more viable and manufacturable solutions (that by the way both IBM and Intel are working on). Again he saw something he wanted to see and tried to fit it into AMD must have a better roadmap conclusion.

And just an amusing one from H2'06:

"On top of this, Intel will find itself with a very disappointing 2006 earnings report and enormous pressure on stock buyback with money that it won't have. It is likely to be faced with the prospect of either spending down its cash even more or watching its stock price plunge. From all of these disadvantages it is clear that Intel is not playing its own game."

He was right about a stock price plunge - just the wrong company...

Giant said...

Check it out:

http://youtube.com/watch?v=F7LNUkHa7U8

September 18th, San Fransisco is the start of IDF. The skull is clearly a reference to Skulltrail.

Axel said...

Anonymous

If they just raised ASP's a bit and let market growth compensate for share loss they would be selling near the same amount of chips at a higher price.

Not exactly. Remember that K10 dies are huge and expensive, with lower yields to boot due to the native design. The ASPs have to increase a lot to make K10 profitable to manufacture. But because K10 does not dominate Clovertown, it cannot be priced at a premium.

SPARKS said...

Well, this didn't take long. What, 3 days?

http://www.theinquirer.net/default.aspx?article=42307

SPARKS

SPARKS said...

And, it gets worse.

http://www.theinquirer.net/default.aspx?article=42303

SPARKS

Anonymous said...

"Remember that K10 dies are huge and expensive, with lower yields to boot due to the native design. The ASPs have to increase a lot to make K10 profitable to manufacture. But because K10 does not dominate Clovertown, it cannot be priced at a premium."

In desktop space the dual core versions will be selling in much higher volumes than the quads (much like Intel today) - that is currently where AMD is taking a bath on ASP's (the desktop ASP has fallen 50% over 6 quarters for AMD). In servers your comment is accurate but I don't think it matters as much as desktop.

Servers are ~5% of AMD's unit sales; while important and profitable AMD's overall ASP's are far more affected by desktop (and mobile) mainstream parts. The majority of desktop will remain dual core and K10 could be priced (if AMD chooses to give up the market share crap) a bit higher and perhaps get AMD back into the black. Expect Intel to move the "price war" to the mobile area.

BTW - Fudzilla is reporting FASN8 (or whatever the hell the name is) is apparently dead - apparently not too much demand for quad graphic cards setup (not to mention the small power plant required). If 'm not mistaken wasn't the 4x4 just a precursor to FASN8? What it was a dual core server bastardized into a dual core desktop bandaid? I though AMD had a plan with 4x4...

Can't you recall all the Sharikook and Dementia articles on how 4x4 would compete with Intel's glued quads and how when K10 came along it would show the true potential of that platform?!?

SPARKS said...

Gentlemen, especially the anonymous types, who sound as if they bake these wafers on a daily basis, please straighten me out on something.

We all know the Barcelona chip itself is a relatively big die. They’re selling these things as quad cores. Now, if a microscopic monkey wrench screws up one or 2 cores, will they sell this as a dual core processor? If so, does that mean the one good core, of the remaining three, gets disabled, essentially wasting a perfectly good core? Again, if so, assuming 25 percent of all 4 core Barcelonas go bad, does this mean they are disabling 12.5 percent of the wafer with perfectly functional cores?

Further, what happens if all four cores pass, but one unhappy camper is a little slow. Does this mean the fastest Barcelona is only as fast as its slowest core? I know, from my experience with my beloved XE chips that these bad boys were, crème de la crème of the factory sum cum laud. MCM means Intel cut their losses by half, by half, right? How does this factor with Barcelona yields on obtaining a perfectly executed die, factoring in the above variables? In other words, will I get one gem out of a 300mm wafer? Help me out here, I’m still trying figure what this idiots were thinking two years ago.

“I am an Electrician, Jim, not a brick layer.”

SPARKS

Anonymous said...

"Further, what happens if all four cores pass, but one unhappy camper is a little slow. Does this mean the fastest Barcelona is only as fast as its slowest core?"

You are limited by your slowest core (in terms of rating and binning it as a 2.0GHz, 2.2GHz, etc...). However K10 does have the ability to independently clock the cores (not sure if this is user controllable). A smart user may be able to squeeze this performance back out thru overclocking the capable cores? (Again not familaiar enough with the architecture at this point to understand if this is user controlled)

This concept however is one SIGNIFICANT advantage of MCM solution as you can pair up like chips instead of downgrading the bin to the "lowest common denominator" - this really helps with bin splits. Similarly with power this also helps, if you are trying to produce low power chip versions, you can pair two low power die together or if you have an extremely "leaky die" you may be able to pair it with a low power one and still meet the overall MCM TDP.

As for your question about diasbling cores I don't know. Intel has definitely done this with cache as they have the ability to fuse off bad portions of the cache. In theory you should be able to do this with K10 but I suspect it would be harder as the HT links may complicate matters. Also if you cannot fully disable the bad cores (if for example you need the HT link) there may also be a power penalty for doing so (your TDP would now be more than just 2 cores worth of transistors)

As for yields that is a very complex issue. For purely random defect yield issues MCM is superior as one defect kills one dual core (or 1/2 of an MCM) while one defect would kill an entire native quad. So in theory you could have TWICE as many random defects on an MCM process and get the same # of good quad cores out of the wafer.

However this is oversimplified - not all yield issues are due to random defects - many can be process limitations (ex: am marginal etch process may cause an incomplete etch and a short or open where you don't want one) and these are not usually random in nature. Also in the case of non random particle issues you may get 2 or 3 killer defects on the same quad.

The benefit of MCM on the process window side is that as the die is smaller the overall process variability within the due to normal process variations on a wafer (for example CMP may polish faster on the edge of a wafer leading to more Cu overpolish and more resitivity at the edge). With a smaller die the probabality of adie being out of a process spec range is generally smaller than a larger die.

So in short the best possible advantage of MCM is to lose 1/2 the die a "native" solution would, but this won't happen in the real world as all yield defects are not truly random or particle related. MCM does provide much more flexibility and a larger process window for yields and binsplits though (in my mind this is the more significant advantage)

Anonymous said...

One addition - it is amazing what can be done now after the fact in terms of "fusing" chips (different areas/metal layers can be cut and altered after processing is done).

Intel in the past has disabled working parts (I assume to meet demand and simplify things by not having to have maintain 2 different mask sets).

Most of the original Core2 desktop chips (all?) were processed with 4MB of cache and just because some chips were 2MB don't assume the other 2MB cache was bad. Also clock speeds can actually be downbinned (turn a 3.0GHz chip into a 2.6GHz), while it doesn't sound right, it actually makes some sense if you have a shortage at one bin - the cost of producing the wafer whether is the same whether you are trying to make a 3.0GHz or 2.6GHz chip, it just a matter of how many chips you get at each of the bins (obviously you typically get fewer high speed chips).

As for what AMD was thinking - people just state MCM as a simple gluing of 2 chips in one package - it's a bit more difficult than that. Intel has been doing this for some time - MCM dates back to the original Pentium Pro days. In AMD's case it is actually probably harder because they also have to deal with the IMC. If it really were a simple task and a 3-6 month thing (like I've heard some people ridiculously suggest!), we would have seen MCM K8's by now.

AMD made a gamble on native on 65nm - if I had to speculate I think they must have assumed the scaling penalty of MCM was going to be worse than it turned out to be and therefore a native solution would dominate an MCM version (and therefore could be priced higher to offset the higher manuf costs). They also completely misjudged the market - especially server where the extra cores provide real tangible benefit today.

I think Intel's strategy is better - when things get to 45nm the die size will be small enough where wafer variation effects and random defect yield will be far less of an issue with the smaller die size. The other potential issue with AMD is their CTI (continuous transistor improvement) approach vs Intel's pretty much put all of the improvements in at start of the ramp. The strain technologies are very pattern sensitive and I think this will be a nightmare for AMD if they plan to continuously tweak this process (to get better transistor performance--> clock speed) with such potential for large variation on that big die. By the time Intel does native quad on Nehalem that 45nm process will be DONE and have been running for ~ 1 year.

CTI sounds great on paper but it's hellish from a manufacturing perspective APM3.0 or not!

SPARKS said...

Anonymous 'CHIP GURU', Thankyou!

BRILLIANT, simply, brilliant!

Sincerely-
SPARKS

Roborat, Ph.D said...

sparks said: Now, if a microscopic monkey wrench screws up one or 2 cores, will they sell this as a dual core processor?

they can't. you have to consider the entire die, even though a QC, as a single device. a catastrophic defect to a single die normally has reliability implications (i.e. behave abnormally, drift in performance over time, consume more power). non catastrophic defects (i.e., slower bin) is another matter.

Further, what happens if all four cores pass, but one unhappy camper is a little slow.

it would be interesting to find out how AMD clock their multi core CPUs. I would guess it would be a mean value rather than max or min clock.

MCM means Intel cut their losses by half, by half, right?

The idea that Intel can cherry pick bins and combine similar clocked CPUs is a myth. Intel (nor AMD) cannot tell what the speed of the CPU is until it is packaged. Therefore it is too late for cherry picking.

Bump and test facilities can only determine known good die (KGD) without knowing how it will perform. The advantage of an MCM approach lies mainly on the avoided yield loss associated with a much larger die. But by all means this isn't insignificant.

Anonymous said...

Not really a guru - just someone with a bit of a background, as opposed to the posers like Scientia, Abinstein and Sharikou.

I really want people to know that ANYTHING those folks say regarding process technology and manufacturing should be taken with a HUGE grain of salt as they make some egregious errors. I have in the past tried posting a counterview (and supported with data/links) and they either decide not to post it or move the discussion to some other point, rather than acknowledging the error (Abinstein in particular does this). As such I have given up posting on their sites but still read them for the entertainment value.

Scientia forecasting that AMD being 6 months behind Intel on 45nm is by far one of the most absurd and hilarious comments I've read in a long time - especially as he completely screws up shipping vs availability dates and ignores the underlying technology capability of the process (this is essentially like saying 2 chips with 2 different architectures operating at 3 GHz are equivalent).

From someone who understands the tech, Intel is still at least 2 years ahead of IBM/AMD mainly due to highK metal/gate (Intel has integrated a high performance version of this which is already yielding and going into manufacturing while IBM has been vague about when they will implement and on what products and has only demonstrated proof of concept). What is less well known is Intel still has significant technical advantages in salicide, and implant anneal areas which are overlooked and not generally reported on in the industry as most folks just like to look at timing of 45nm and SOI vs bare Si. What is humorous is despite many folks saying SOI helps reduce leakage over Si (which it does), Intel still has lower Ioff (off state transistor leakage) values for a given Ion at an equivalent technology node- this data is pubic (IEDM).

Funny how Intel could do this with less advanced technology like bare Si...makes you wonder, no? This is mainly due to the fact that Intel's front end process is far better and more than makes up for any advantage SOI has (and doesn't incur the added cost of using a more costly susbtrate). Ultimately it comes down to integrated process performance, not nice press announcements like SOI, immersion litho, or ULK ILD's.

Just don't get me started on immersion...

Anonymous said...

"it would be interesting to find out how AMD clock their multi core CPUs. I would guess it would be a mean value rather than max or min clock."

I don't see how AMD could get away with an average - why would quad be any different than current dual core binning? What would happen when people use SW that is not capable of using multiple cores? (especially when desktop chips versions come) Would the chip, bios and/or OS somehow know the fast core vs the slow core? I would tend to think AMD would have to use the minimum of the 4 cores, because for a single threaded applictaion the end user would be a bit diappointed if it is running on the "slow" core and performing the same as a chip one speedbin down.

I guess they could come up with a new clockspeed benchmark and call it average virtual clockspeed (much like the crap they are trying with power!) They could run multiple SW types and come up with an "effective" clockspeed!

SPARKS said...

Whew! Give me a 4 6000A services in a major building in Manhattan ANY day. Throw in fuel cells, the buildings network hub, the FACP, and building management controls, for kicks and giggles.


“Strain technologies are very pattern sensitive.”

“Intel’s Significant technical advantages in salicide, and implant anneal areas.”

“Integrated process performance, not nice press announcements like SOI, immersion litho, or ULK ILD's.”

“People use SW that is not capable of using multiple cores?”

“Don't get me started on immersion”

Ok, I’m developmentally disabled. I read these enlightening piece(s) 3 times! I’ll have to do some homework around the web to basically understand these processes.

But, I do know this. You have been correct all along, DOC and GURU. AMD’s native quad core implementation at 65nm was, and maybe still is, technically and economically unfeasible, presently. Perhaps, with a refined process and a proven architecture in conjunction with 45 and 32 nm, with high yields and high speeds, a successful native quad core can be achieved. NOT by AMD, however, certainly, not in their current financial position.

Is there an axiom that states ‘never compromise on yields?’ Or, ‘never try to implement a new architecture and a new process at the same time’? If there isn’t, there ought to be.

1. As I see it, if one of Baby B’s Cores comes off the line with a flat, you must junk the truck.

2. If all the guys in the crew don’t play nice and work well with others, the whole crew will slow down, maybe walk off the job.

3. If the jobs starts even with the best prints, if you don’t get the right materials, that pig ain’t gonna fly anyway, no mater what you do.

4. You guys didn’t factor in voltage, heat and frequency into the mix, much as you did leakage. I’m guessing, but they must only exacerbate the leakage issue further. (“Anandtech's review of a 2.5GHz ES was running at 1.52Volts”) was a clue, was it not?

5. You guys saw all this coming months ago, if not a year ago, WHY, therefore, didn’t AMD’s big Cahoona’s ???

Oh, yeah, GURU, about the immersion thing, please, feel free. Sounds like you want to get it off your chest anyway. Your tech analysis is worth more than 2 dozen ANAL-ysts, any day. I, and others, are getting an education. After this insight into chip fabrication and analysis, I can only see INTC going one way. UP! Shall we say, low 30’s 2Q ’08?


THANKS!

SPARKS

SPARKS said...

From Anandtech, confirming the above supposition:

"If there was ever any doubt that Intel made a bad decision not going true quad-core, it should be clear with numbers like these that their decision was sound and is paying off. Quad-core processors may not be faster in every situation, but in heavily threaded CPU intensive environments the extra CPU cores are easily able to make up for any penalties associated with the dual-die packaging"

http://anandtech.com/cpuchipsets/
intel/showdoc.aspx?i=3095&p=8

Bravo, GURU, and DOC. Well done!

SPARKS

Anonymous said...

It may be speculated that AMD is only yielding K10 at a jaw-dropping 30%. 30%!!

Based on AMD's published data, which claimed 0.5 defects density, and coupled with yield management chart, it can be concluded that AMD's K10 are yielding at no more than 35%.

AMD's Data:
http://www.iian.ibeam.com/events/thom001/22876/browser/slides/20070726084721294707/default_large/Slide158.JPG

Yield management by ICEC
http://smithsonianchips.si.edu/ice/cd/CEICM/SECTION3.pdf

If you scroll down to Figure 3-9 in Yield Management, you can see the chart. Follow the 0.5 density defect rate to 280, then....

Anonymous said...

"5. You guys saw all this coming months ago, if not a year ago, WHY, therefore, didn’t AMD’s big Cahoona’s ??? "

The problem is Barcelona design was started YEARS ago not months ago. They were betting the farm that it would be far superior to Intel's quad (look no further than the at least 40% better on average over Intel's best chip). Scientia goes so far as to say AMD didn't see Intel's quad MCM coming until too late - I highly doubt this given Intel's ability to do this MULTIPLE times in the past. This is just Scientia being an AMD apologist (again) instead of questioning why AMD's top mgmt has such poor strategic vision and can't anticipate competitor's moves.

It's also possible AMD did in fact see the issues coming (except maybe the stepping and clockspeed issues/delays) - but realistically what were they going to say - they were committed to this course barring a TOTAL failure. These are the same guys who at end of Dec last year said everything's on track financially for the quarter and then only weeks later warned of a MAJOR revenue shortfall. (Are they really that incompetent? I find it hard to believe)

BTW - I think the axiom you are looking for is KISS (Keep It Simple Stupid!). Intel is more than willing to tradeoff off elegance vs manufacturability (see MCM, see pushing out immersion an extra node, see not using SOI...) - this is the sign of a MANUFACTURING COMPANY. Similar to IBM, AMD is an engineering company and sometimes that doesn't coincide with manufacturing excellence. Occasionally an engineering company will excel (when AMD have a superior product like K8), but over time it is difficult to ALWAYS have a superior design and then manufacturing becomes the key determinant of success.

KISS also comes into play with Copy exactly - folks who don't understand manufacturing bad mouth this approach and call it archaic compared to some vague concept called APM (which by the way Intel and every other IC manufacture uses a form of). But would you rather have a process that is designed to have a relatively wide window that will work in any fab anywhere using the same process recipes or one that you tweak on the fly or from tool to tool to eke out a little performace.

While the tweaking sounds great and may seem more efficient as you are potentially getting every little bit out of your process, what happens when you have a fab excursion and tools are running different recipes or are configured slightly differently? You have MANY variables in the fab and several hundred process steps and minimizing as many variables as you can makes it easier to troubleshoot when the inevitable excursion comes up.

By the way quad core is not technically infeasible on 65nm, it's just a matter of economics. Intel's Itanium on 90nm (and maybe 130nm?) was a huge die - Intel offset this with the high price of these chips. I have little doubt AMD will be able to scale K10 to 2.8-3.0GHz on 65nm by sometime next year (maybe even more), it's just a question of at what cost and will that product be superior to Intel's product to justify the higher price?

pointer said...

Roborat, Ph.D said... The idea that Intel can cherry pick bins and combine similar clocked CPUs is a myth. Intel (nor AMD) cannot tell what the speed of the CPU is until it is packaged. Therefore it is too late for cherry picking.


In general, what you said are correct. The frequency binning is only happening during the test (at test site, after assmebly), not sort (at fab).

Nonethelss, as what the anonymous aid, intel can match a leaky die with a better die to form QC that meeting the TDP requirement. I guess intel can predict the leakiness of a fab lot base on its skew parameters, or may be the sort would have some data that help indicates that. (anonymous can correct me here, I have never worked in a fab, though through my career, i dealed with fab before)

pointer said...

Anonymous said...
...

Well Intel demoed one Conroe processor at 2.93Ghz almost 2 years ago….. Guess what? Intel is at 3.0Ghz today!!!! An 70Mhz clock increase!!! Amazing!!!
But forget this, Intel is superb and AMD sucks it’s easier to say.


wow, by you definition, AMD will do a AMAZING 50% clock increase when it finally reelase 3GHz?? :) May be AMD should have released 1.5GHz so that you can claim a WHOOPING 100% clock in increase within a year?? :)

Anonymous said...

5. You guys saw all this coming months ago, if not a year ago, WHY, therefore, didn’t AMD’s big Cahoona’s ???

As anon poster said, I think that AMD had to choose a particular approach and once they did they didn't really have the time or resources to change it very much. They bet the farm and had to stay the course and do the best they could.

I don't think it's the first time they've gone out on a limb, and I'm worried that it could be the last.

Anonymous said...

Please add Christian Howell's name to the list of people who should not be commenting on technology and manufacturing:

"This means that their largest segment is 200mm @90nm. Gong to 300mm @65nm provides >3X the amount of chips even with Opteron as 223mm vs 283mm is only 25% larger with 150% more die space."

First off Opetron is ~5% of AMD's UNIT sales (of course it represents more if you do this by revenue).

2nd how the heck do you get 3X? Instead of breaking out a die calculator (I'm lazy) - let's say AMD gets 100 Opteron chips @90nm on 200mm wafer... if you increase the size by 25% you now have ~75 chips (again too lazy to calculate this).

Now let's go from 200-300mmm which is 2.25x by area (we'll use 2X...because I'm lazy)

This would give AMD ~150 die per wafer on K10 quad core 65nm/300mm vs 100 Opteron die/200mm wafer - how is this a 3X die increase...this damn AMD fanboy math is pretty amusing.

Now let's look at the massive cost savings associated with this! Well it cuts AMD cost by ~33%, no? More die per wafer = good, right!?!

Well there is this slight complication of a 300mm wafer costing more to manufacture than 200mm. Oh and moving from 90nm to 65nm isn't quite "free" - they have these extra metal layers, extra strain steps, more aggressive litho...these things believe it or not tend to cost some money! (I know, it's a crazy world!)

Most sematech benchmarks puts 300mm savings at ~30%, not near 100% as most people blindly assume as they are confusing the added CAPACITY of getting 2X the die vs the cost of MANUFACTURING the die.

How about 90nm to 65nm - in general a tech node transition may add anywhere from ~10-15% to the overall wafer costs. Obviously if you are able to reduce die size this is still a good trade even with AMD's POOR scaling on K8...

So on server side AMD is getting ~50% more die per wafer (probably closer to 75% due to all of the rounding and laziness on my part on the math). However the processed wafer cost has gone up ~70% thanks to 300mm and another ~10% thanks to 65nm.

Now I'm not a math whiz but what do you guys think is happening from a cost savings point of view, especially on the large quad core die?

So why would AMD do this, they're not really this stupid if my numbers are correct? Well for dual core they will see significant cost savings (comparing 90nm/200mm dual core to 65nm/300mm dual core you'll see >130% more potential good die per wafer). And as many have commented here the dual core yield will be better on 300mm (assuming 65nm is not broken) as the die size is smaller thanks to the 65nm shrink (again comparing dual core to dual core).

Just keep in mind the native quad cores are not the massive money makers for AMD that everyone thinks (unless AMD can price them high enough). They would need to be at least 2.5-3.0X the dual core price to provide the same margin when you consider the die size and yield impacts.

Financially,it is better for AMD to sell a ~$100 dual core chip then a $200 quad core chip. So if AMD keeps cutting the mainstream ASP's (to get market share and "break the monopoly") and hopes the high end server ASP's will offset that, well they will be heading for more losses. The real question will be how do they price the dual core K10's in the desktop space! If it's more slash and burn they will continue to fight to eke out survival. if they price them higher (and possibly lose some share) they will be far better off in terms of profits.

SPARKS said...

“I think the axiom you are looking for is KISS (Keep It Simple Stupid!).”

Ah, Kelly Johnson, of the Lockheed ‘Skunk Works’ fame, the consummate engineers’ engineer, coined the K.I.S.S.

His baby was the SR-71 Blackbird, AKA Namu, the overclockers’, overclocker. Clocked in at a, still classified, Mach 3+, still holds the absolute worlds speed record for an air breathing Aircraft at 2193.167 MPH, to this day. HOO YAA!

http://www.marchfield.org/sr71a.htm


There was another engineer; his name was Edward A. Murphy. I don’t think I need to tell you guy’s about this gentleman. I’m sure you’ve dealt with his principles before.

http://en.wikipedia.org/wiki/Edward_A._Murphy%2C_Jr.

In addition to his most famous axiom, there was another. I think it applies very well to the AMD and INTC Quad Core design approach.

"If there's more than one way to do a job, and one of those ways will result in disaster, then somebody will do it that way."

SPARKS

Roborat, Ph.D said...

pointer said: Nonethelss, as what the anonymous aid, intel can match a leaky die with a better die to form QC that meeting the TDP requirement.


this isn't possible. the distribution curve of leakage is extremely exponential. you either get a device within limits or you get ones that are way off. there are no varying degrees and definitely no method for binning for leakage. the requirements for an accurate metrology tool would be insane since we're talking about ~nanoAmp levels.

Anonymous said...

"the requirements for an accurate metrology tool would be insane since we're talking about ~nanoAmp levels."

Robo while I'm not diagreeing with you conclusion regarding binning with power, the metrology to do this measurement is not insane - it is rather simple to devise a test structure and measure leakage (which with should be able to be correlated to TDP with enough data). These are very typical on on test vehicles and I believe at one point some IC manufactures had them in test structures printed in the scribe line on real production wafers for inline metro (though I think this was more a pass/fail metrology for the inline work)

For small structures you are talking about measuring AMPS/cm2 (because the structures are so small) - this is not difficult for a simple probe tool with a C-V measurement. I don't think this is typically done on product wafers but it theoretically could be on the inactive scribeline test structures.

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