tag:blogger.com,1999:blog-2602471396566186819.post279219726327930999..comments2023-10-26T15:06:30.940+00:00Comments on AIMeD Corporation: The Game of Leapfrogging Needs At Least 2 FrogsRoborat, Ph.Dhttp://www.blogger.com/profile/04845879517177508741noreply@blogger.comBlogger62125tag:blogger.com,1999:blog-2602471396566186819.post-86353274205234685292008-01-25T07:21:00.000+00:002008-01-25T07:21:00.000+00:00Robo knows all about leapfrog, lol. He is great wh...Robo knows all about leapfrog, lol. He is great when he's on top or when he's on bottom. Of course it was more banging than leaping. Bring the vaseline!Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-64266238074650580792007-11-06T11:34:00.000+00:002007-11-06T11:34:00.000+00:00"Technological advantage"? Their best part is cur..."Technological advantage"? Their best part is currently slower than their primary competition's mid-range product!Tonushttps://www.blogger.com/profile/01082528970434639776noreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-70794792921268128172007-11-06T06:37:00.000+00:002007-11-06T06:37:00.000+00:00"at least AMD still has its graphics division to f...<I>"at least AMD still has its graphics division to fall back on"</I><BR/><BR/>I wonder how it works with having around $200M total revenue and millions of losses for graphics division in last quarterHo Hohttps://www.blogger.com/profile/00177815588184912351noreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-15912487156349208572007-11-06T05:24:00.000+00:002007-11-06T05:24:00.000+00:00From the previous link:"Unfortunately, it's becomi...From the previous link:<BR/><BR/>"Unfortunately, it's becoming clearer and clearer why a triple-core version has become a necessity - at least then there's more chance of cores with a decent clock speed. A weak core in any quartet can simply be disabled and a triple-core CPU created."<BR/><BR/>Unfortunately it's becoming clearer and clearer that the press has nary a clue about Si processing and how things work. (Though it is fun to watch these folks with no background commment on it ala Scientia. Of course Scientia is at least doing it in an AMD fan blog, these "journalists" are spreading it more under the guise of truth).<BR/><BR/>Tri-Core is about YIELD, not binsplits! With the exception of the very edge of the wafer you will not have wild clockspeed swings from core to core. The cores may have binsplit (clockspeed and/or power) issues in general but these would be limited by specific speed paths inside a core or global process variation. <BR/><BR/>For quad cores you are talking 283mm2 - lets sat 20mm x 14mm for argument's sake. Now that puts each core at ~10x7 mm - do you really think there is that much clock variability on cores 10mm apart? <BR/><BR/>Again, tri-core is a reponse to YIELD (non-working) issue, there may be MARGINAL power or speed benefits but it's not like you have quads with 3 cores operating at 3.0GHz and 1 core working @ 2.4GHz, therefor you can magically turn on e off and get these great clock increase - that is not what is the cause of the low clockspeeds on the quads... <BR/><BR/>...the problem is power - look at the relatvely low Vcore on the ES of the Phenom chip - this is lower than Intel's typical 65nm Vcore, and yet they were only operating at 2.4GHz (or 2.3?). AMD should (theoretically) be able to increase the Vcore and get better clocks - the fact that they don't (or can't?) leads me to believe that power goes out of control with higher Vcores (which could be either a design or, in my view, more likely a 65nm issue given AMD's inability to get even K8 clocks up on 65nm).<BR/><BR/>It is interesting that the underdog, let's give AMD the benefit of the doubt, press coverage is starting to go away.<BR/><BR/>And the kicker in the article:<BR/>"Oh well - at least AMD still has its graphics division to fall back on. That's one area where AMD does have a technological advantage in manufacturing over its major competitor.'<BR/><BR/>AMD does use a foundry for ALL OF THEIR GRAPHICS PARTS...Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-50791150171600301882007-11-05T21:50:00.000+00:002007-11-05T21:50:00.000+00:00Phenom Disappointmenthttp://www.tech.co.uk/perform...Phenom Disappointment<BR/><BR/>http://www.tech.co.uk/performance-pc/general/blogs/2007/11/05/phenom-disappointment<BR/><BR/>clock for clock comparisons show Phenom can't compete with Penryn.<BR/><BR/>Abinstein, Scientia, and others busy working with AMD to come up with excusesAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-49425546042236268082007-11-05T17:07:00.000+00:002007-11-05T17:07:00.000+00:00let me preview the next hot topics over at Amdzone...let me preview the next hot topics over at Amdzone:<BR/><BR/>"Crysis is unfairly optimized for Intel processors."<BR/><BR/>"The 3GHz Phenom is unfairly disadvantaged because it's memory clock is running at 350MHz."<BR/><BR/>"Phenom is unfairly disadvantaged because it's L3 cache is only 2MB."<BR/><BR/>"C2D cheats at benchmarks because single-threaded processes can use the entire 4MB/6MB cache."<BR/><BR/>"That source, just like Anandtech and Tomshardware, is obviously paid off by Intel."<BR/><BR/>=PAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-20550972800857468842007-11-05T14:09:00.000+00:002007-11-05T14:09:00.000+00:00More evidence that in games, Phenom X4 will be sig...<A HREF="http://www.expreview.com/news/hard/2007-11-05/1194231291d6785_1.html" REL="nofollow">More evidence</A> that in games, Phenom X4 will be significantly slower than Kentsfield per clock, even at 3.0 GHz. Rahul Sood's claim from a couple months ago that Phenom 3.0 GHz would "kick the living crap" out of any processor then on the market will soon be proven to have been utter unfounded fallacy.<BR/><BR/>We can see that Crysis gains significantly in performance going from K8 dual core to K10 quad core, yet even the Intel dual core E6850 <A HREF="http://www.expreview.com/img/news/071105/hybrid_platform.png" REL="nofollow">beats Phenom X4 clock-for-clock</A>.Axelhttps://www.blogger.com/profile/15126742407361053721noreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-86964691272643519432007-11-04T23:49:00.000+00:002007-11-04T23:49:00.000+00:00I was under the impression that it's been the INQ'...I was under the impression that it's been the INQ's policy not to sign NDAs. It's not as bad a policy for them as you might think, since they're a news site and not really a hardware review shop.<BR/><BR/>If they didn't sign the NDA to be allowed to get pre-release CPUs from AMD, it probably isn't because they felt AMD was running a dirty deal, but because of their own policy.Tonushttps://www.blogger.com/profile/01082528970434639776noreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-64265494253806703902007-11-04T18:05:00.000+00:002007-11-04T18:05:00.000+00:00"I already explained that. A larger die will have ..."I already explained that. A larger die will have more defects and therefore worse binning"<BR/><BR/>Apparently Dementia doesn't understand the difference "binning" and yield as somone else noted earlier in this blog. More defects means yield issues (nonfunctional die). Bigger die doesn't necessarily mean worse BINNING unless you have a process that is crap (AMD 65nm) or a design that is on a cliff with respect to the process (K10).<BR/><BR/>Intel designs the processor with manufacturing in mind, AMD designs and then tries to figure out how to make it. You can mock Intel all you want for an inferior FSB design, offboard memory controller and MCM.... but these were all design decisions made with manufacturng, cost and time to market in mind. I would expect Nehalem to be the same - if it were not manufacturable then Intel would stick with the "inferior" FSB designAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-46533309306904115022007-11-04T17:56:00.000+00:002007-11-04T17:56:00.000+00:00"I think he has just proven the anonymous poster's..."I think he has just proven the anonymous poster's point." (regarding Dementia)<BR/><BR/>His latest comments:<BR/><BR/>"We haven't yet seen AMD's 45nm to know what type of power saving it might have. Intel's 45nm could be a lot better or only slightly better. I do expect Intel's to be at least some better. If Intel's is a lot better then AMD may decide to go with high K on 45nm afterall in 2009."<BR/><BR/><BR/>Hmmm.... this goes to my last point about trying to understate AMD's capabilities so he can talk them up later... He is now EXPECTING AMd's process to be AT LEAST "a little worse" and hold out the possibility of "much worse". In so doing he has layed the foundation for the inevitable future comment - I expected AMD to be far worse and things are better than expected! Much like K10 performance and clockspeeds - he now calls the Phenom speeds EXPECTED? He didn't say AT LEAST 2.6GHz in Q4, if not possibly 3.0GHz in Q4?<BR/><BR/>Why would AMD be worse on 45nm, I mean they do have SOI and immersion right? Oh yeah those things are PR which have no real gain attributable to them (especially immersion)... AMD will get some gains from the overall Vt (transistor threshold voltage) reduction on the tech node, however with the lack of scaling of the gate they will have a difficult reducing it and Vcore significantly without the leakage problem growing (exponentially). SOI or immersion <BR/>will do NOTHING to the physics on this! So AMD has the devilish choice of low clockspeeds with reasonable TDP's or higher clockspeeds with high TDP's (see AMD 65nm process and K10 for additional learnings!)<BR/><BR/>As for AMD using high K in 2009 if Intel turns out to be much better (which by the way they will be) - it's not like AMD can just simply CHOOSE when to implement this technology. It involves new tools to be put in the fab, new integration, reliability testing, etc.. If AMD could do this in 2009 they will - it's not a matter of 'we have it in our pocket and we'll see if we need it' Ok guys turn on the old APM3.0 high K switch looks like we need it - you;ll have that ready to go later today, right?<BR/><BR/>Just what is AMD supposed to do in their fabs for 45nm - do they leave space for these tools in case they need them (which would mean potentially an inefficient fab layout if they don't get around to it). Do they spend the extra money now and put the tools in (yeah like AMD has that cash to burn right now). This is yet another one of the huge differences between the CTI AMD approach and the Intel get it done before you ramp approach.<BR/><BR/>The problem with just inserting high K, is it changes MANY steps in the processing it's not just the actual step to deposit the film! You are talking new equipment, chemicals, integration, testing structures, and many changes to numerous implant, anneal and other front end steps.<BR/><BR/>Why would AMD do this? It only makes sense if you do it on the bulk of the technology node. - Dementia has claimed AMD will continue to be on an "accelerated" (in his world) schedule and will have 32nm in early 2010 to further close the gap with Intel, so they will use high K on 45nm for what 6 months (?) and then be forced to re-tune it for 32nm?<BR/><BR/>When I read well, frankly, ignorant comments like these I wonder if he is aware of his lack of knowledge and is intentionally trying to mislead people or if he just doesn't understand the complexities of these things and thinks things are really as simple as he believes them to be. Either way it is pretty damn funny!Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-45675856131811571772007-11-04T16:56:00.000+00:002007-11-04T16:56:00.000+00:00“Not all of the third party sites agreed to the ND...“Not all of the third party sites agreed to the NDA - folks like the INQ, flat out refused it as they knew why they were being asked to sign it.”<BR/><BR/><BR/>The INQ and its staff weren’t that altruistic from the beginning. The first to show their disenchantment with AMD was Digitimes. This was before the NDA fiasco. INQ’s reaction came later.<BR/><BR/>As you probably know, the INQ were vehement AMD supporters for years. Nearly the entire staff had the “Scrappy Little Company”, underdog, monopolistic, and Evil Empire thing going on. Further, with Henri Richards marketing strategy of, very effectively, courting the press, AMD was for years, the darling of the press.<BR/><BR/>The time line was revealing during the second half. Basically, AMD was in panic mode. AMD had pumped the press very badly since 2006. The press (Read: INQ) reported ANYTHING AMD said, wrote, and ejaculated. When it came time to confirm all the spin, the press woke up and realized they were taken for a ride and their integrity had been compromised. They kept quite about it hoping for an AMD miracle. It never materialized.<BR/><BR/> It wasn’t until industry veteran Mike Magee, editor of the INQ, called AMD directly to get some information. Well, shall we say he wasn’t treated like the pompous Industry veteran we have come to love and admire? He said, in so many words, ‘they nearly bit his head off’. <BR/><BR/>About the same time, he received the bad news of the AMD NDA. I believe this threw him over the edge. He did an editorial that week blasting AMD. The Fanboys were in a rage as he tried to maintain/regain editorial credibility. He has since toned down his Anti Intel stance. Unexpectedly, in this months CPU magazine, he is calling for INTC to enter the graphics market and put an end to the “cartel” of high priced AMD/ATI GPU”s. Personally, I saw him throwing Intel an olive branch.<BR/><BR/>In any event, with Henri Richards’s departure, Digitimes drawing first blood, and Mike Magee maintaining editorial integrity, AMD’s free fide with the press has come to close. They have all followed suit. That said, the tech press is far from actually criticizing AMD but the ‘flavor’ of their reporting has become a bit more objective. Besides, to quickly do an about face would be admitting to erroneously publishing all the spin and Power Point Presentations AMD hyped for nearly a YEAR. <BR/><BR/>Further, I believe the financial community is in the same predicament. However, this has to do with something a bit more substantive than editorial license. <BR/><BR/>We’re talking MONEY, BIG MONEY! Someone, somewhere, WILL be held accountable for losing all those billions, especially in the financial institutions. The Barcelona/ATI fiasco has only just begun. I wouldn’t be surprised AMD executives wind up in court explaining why they mislead investors with months of false claims. <BR/><BR/>SPARKSAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-58992139792054940002007-11-04T16:02:00.000+00:002007-11-04T16:02:00.000+00:00Anonymous said...Honestly Scientia know squat abou...Anonymous said...<BR/><I>Honestly Scientia know squat about Si processing, I don;t think he is confusing it with a parametric issue as he likely has know clue what that is!</I><BR/><BR/>In support of which Scientia said...<BR/><BR/><I>I already explained that. A larger die will have more defects and therefore worse binning. Also because it is monolithic Intel can't do die pairing as they do with MCM quads.</I><BR/><BR/>I think he has just proven the anonymous poster's point.InTheKnowhttps://www.blogger.com/profile/16869163385384973596noreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-50769109480167144942007-11-04T08:27:00.000+00:002007-11-04T08:27:00.000+00:00I love how whenever Scientia comments on some new ...I love how whenever Scientia comments on some new technology from Intel, he is quick to point out how the new technology negates a positive factor in Intel's favor from the past, so essentially Intel has taken 1 step forward and 1 step back.<BR/><BR/>Like how Penryn's SSE power will make it unattractive because of high power draw so all of a sudden Griffin will be so much more competitive (<I>To compete with Puma, Intel does have Penryn however the greater SSE performance of Penryn can only be used with much higher power draw. Some have suggested that Intel could market this as both a notebook and desktop replacement. The problem with this idea is that desktop replacement units (like I use) have brighter displays, larger speakers, larger physical size, and greater weight. You really can't get a desktop replacement without making the unit less portable.)</I>.<BR/><BR/>For Nehalem, Intel will of course lose its advantage in die size, power consumption, large cache size, and Nehalem's longer pipeline will absolutely make it not much better than Penryn. (<I>If Nehalem has a longer pipeline it may indeed have a faster clock but this would still mean a slower processor. I'm simply not expecting the initial Nehalem's to be faster than Penryn (which should be pretty fast by that time).</I><BR/><BR/>Of course, whenever AMD announces something (DTX, SSE5 - hey, it's one of the top developments of 2007!), it is supposed to have some huge impact on the industry.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-81736119513662571962007-11-04T05:14:00.000+00:002007-11-04T05:14:00.000+00:00This is my favorite part of Scientia selective mem...This is my favorite part of Scientia selective memory:<BR/><BR/>"AMD may not hit 3.2Ghz on 65nm until Q4 after Shanghai has already been released on 45nm."<BR/><BR/>He's been stating 3.0GHz potentially by end of year and DEFINITELY in Q1'08 for AMD. Now he sees no further improvement beyond that until Q4? Heck AMD demo'd a 3.0GHz part and we all know AMD doesn;t cherrypick or overclock parts for a demo - forget the fact that AMD wouldn't ley anyone look at the system to see what voltage they were using or measure the chip's TDP! His twisted logic is starting to unravel.<BR/><BR/>Let me edit his comment as I think he meant to say "AMD may not hit 3.2GHz on 65nm **EVER**" (for quad core). Heck 45nm will be a challenge as AMD will be unble to scale the gat oxide any on 65nm so they will have to do some spectacular things with implant and anneal or jack the voltage (which means worse TDP's and probably even worse bin splits)<BR/><BR/>It's funny he has become like a politician - he understates everything about AMD's roadmap so he can say they met/exceeded it and he intentionally overestimates Intel's roadmap so he can say they are behind or late. Suddenly AMD getting 2.6GHz parts out the door by end of the year is execution to plan (this was the top speed planned for LAUNCH "mid-year" right?). Intel's launch of "only" a 3.16GHz 45nm part initially of course is a disappointment.<BR/><BR/>And how is Intel releasing 45nm in Q4 mean 45nm is slipping/late? Intel repeatedly said H2'08 for 45nm product availability (not ship to OEM crap, who know when it will hit the market that AMD sandbagged with on 65nm). 45nm is also out <2 years after Intel released 65nm products which is AHEAD of the standard 2 year development schedule for a tech node transition. Intel also inserted high K/metal gate one technology node ahead of all major semiconductor roadmaps (such as ITRS). But I guess they are late/behind schedule!Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-6196730851599214022007-11-04T04:56:00.000+00:002007-11-04T04:56:00.000+00:00"What Scientia seems to be referring to is good di..."What Scientia seems to be referring to is good die as a function of die size. That has very little to do with speed bins. He is confusing a particle event with a parametric issue."<BR/><BR/>Honestly Scientia know squat about Si processing, I don;t think he is confusing it with a parametric issue as he likely has know clue what that is! <BR/> <BR/><BR/>Let me see if I can crawl into the mind of the great Dementia - AMD having yield and binsplit issues on 65nm K10... AMD is great so how could this be? What is one difference between AMD and Intel (other than manufacturing know how, and Si process technology) - oh yeah the dies size is bigger - therefore the issue MUST be die size related as there is no possible scenrio where AMD could have an inferior process or yields.<BR/><BR/>Therefore when Intel goes to a bigger die with Nehalem, they have to have similar issues as clearly Intel has inferior manufacturing capabilities and Si technology (I mean heck they're not even using immersion litho on 45nm - they're using cheaper, more manufacturing proven dry litho solutions - how lame is that!).<BR/><BR/>Now for reality - look at the small die size bin splits on 65nm...see any high clock K8 parts? Wonder why that is? Not die size, not new architecture....oh I get it, it must be AMD's CHOICE to do this!<BR/><BR/>As always Scientia takes one observation (die size), lacks a fundamental understanding of things going on around him (process tech, parametrics, bin splits) and tries to fit the one observation into his preformed conclusion (the K10 issue can't be an AMD specific problem)<BR/><BR/>Not sure why you guys even bother with him on these subjects - he is clearly way out of his league on these things and has proven this with his ridiculouts statements and conlusions.... I mean look at one of the last questions in his most recent blog...."Is AMD's faster adoption of Immersion a technical advantage", if he is asking this he doesn't understand lithography and manufacturing costs. <BR/><BR/>Both companies will print the same (or very similar) feature sizes on 45nm. One will do it more cheaply, on proven HVM equipment, and 1 year earlier then the rest of the industry... the other company is AMD. AMD is going to a more expensive, less proven lithography solution BECAUSE they lack the litho technical expertise to extend the 193nm further. <BR/><BR/>Or let me put it this way - would AMD be buying tools that cost nearly 2x more and are unproven in volume production if they could extend their current lithography another generation? These tools are >40Mil PER TOOL! (not that dry litho tools are cheap) I'm sure Intel will be more than happy to let AMD debug the tools, pay the upfront development costs and by the time Intel needs them on 32nm (which unfortunately for Intel in this case won't be that long after AMD is using these on 45nm) the prices should be coming down a bit.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-85007322953208675692007-11-04T04:38:00.000+00:002007-11-04T04:38:00.000+00:00intheknow - the NDA was only for people who wanted...intheknow - the NDA was only for people who wanted an engineering sample early for review. It is obviously ridiculous, but AMD can't prevent a person or company who didn't sign an NDA from buying a product (that's theoretically available now) and writing a review about it.<BR/><BR/>Not all of the third party sites agreed to the NDA - folks like the INQ, flat out refused it as they knew why they were being asked to sign it.<BR/><BR/>I'm wondering why Intel is not taking out a full page ad in the WSJ (ala AMD a few years ago)and challenging AMD to square off with their best commercially available chip against Intel's best to see if it indeeds is 40% better as AMD advertised. Heck Intel should benchmark it as it appears AMD is incapable of benchmarking it themselves (or more specifically afraid to publish the data). At this point I would be shoving all of that native quad core/IMC/HT/4x4 crap right down AMD's throat! Thank you sir can I have another!Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-78105888311798248602007-11-04T03:41:00.000+00:002007-11-04T03:41:00.000+00:00Scientia said..."Intel is also unlikely to release...Scientia said...<BR/><I>"Intel is also unlikely to release Nehalem at speeds faster than 3.2Ghz in 2008."</I><BR/><BR/>To which Peter replied...<BR/><I>And you know this how, exactly?</I><BR/><BR/>And Scientia responded with this...<BR/><I>peter<BR/><BR/> I don't know if you understand about die size and yields. Nehalem will be larger than Shanghai. Nehalem is native quad so it loses die pairing. Nehalem also has a higher ratio of logic to cache circuitry than Penryn. Part of this depends on pipeline length though. If Nehalem has a longer pipeline it may indeed have a faster clock but this would still mean a slower processor. I'm simply not expecting the initial Nehalem's to be faster than Penryn (which should be pretty fast by that time).</I><BR/><BR/>Having Scientia question someone's knowledge of yields is really rather amusing. <BR/><BR/>First off, the discussion is about speed bins (i.e. clock speeds). <BR/><BR/>What Scientia seems to be referring to is good die as a function of die size. That has very little to do with speed bins. He is confusing a particle event with a parametric issue. <BR/><BR/>What will affect speed bins is some sort of error that affects film thickness, film variability across the wafer, litho registration issues, and a host of other things. <BR/>None of which are a direct function of die size. <BR/><BR/>I have no idea what Shanghi's die size has to do with anything, nor do I know how he can say anything about the size of a product that hasn't taped out yet. <BR/><BR/>And I know someone on this site (I'm pretty sure it was Guru) has already shot down the whole die paring thing. You don't know the speed bins until after the die have been paired. <BR/><BR/>The real limiter to Nehalem's final speed will be TDP. And based on what we are seeing out of Penryn, I wouldn't be so sure about Scientia's 3.2 GHz limit.InTheKnowhttps://www.blogger.com/profile/16869163385384973596noreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-2498955168909349082007-11-04T01:40:00.000+00:002007-11-04T01:40:00.000+00:00Well now that the product is "launched" anyone sho...<I>Well now that the product is "launched" anyone should (theoretically) be able to buy a part and review it - the NDA was only for those receiving early samples prior to launch.</I><BR/><BR/>Not if they had to sign <A HREF="http://www.techarp.com/showarticle.aspx?artno=441" REL="nofollow">this</A> NDA. The report is they were trying to push this off on everyone that attended one of AMD's events where details on Barcelona were supposedly revealed. <BR/><BR/><I>First off, the non-disclosure agreement covered everything confidential said or written over the next two years on the product, and had a duration of five years, during which anything published or used in marketing would have to receive written approval from AMD before it could be used. Worse, at the end of the five years, all copies of the information made would have to be returned to the chipmaker.</I><BR/><BR/>If that doesn't provide you the ability to protect your product from any and all criticism I don't know what does. <BR/><BR/><I>You'd also think AMD THEMSELVES WOULD HAVE DONE A FULL SUITE OF TESTING AND PUBLISHED THIS TO THE WORLD to show how good K10 is?</I><BR/><BR/>Which is why I was wondering if they weren't using their NDA to cover for just how many problems Barcelona really has. <BR/><BR/>I just don't buy the idea that the review sites that received a Barcelona sample were "waiting for Penryn" to really bench it. That is one of the more far-fetched ideas I've seen in a while.InTheKnowhttps://www.blogger.com/profile/16869163385384973596noreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-68368029415922060052007-11-04T01:39:00.000+00:002007-11-04T01:39:00.000+00:00i feel ya sparksi feel ya sparksAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-17755932649961875332007-11-03T22:31:00.000+00:002007-11-03T22:31:00.000+00:00"Analysts are supposed to ANALYZE no? They just ta..."Analysts are supposed to ANALYZE no? They just take everything a company tells them and pass it on without questioning it?"<BR/><BR/> Ah, the Anal-ist thing. First and foremost, let’s get one thing straight. If anyone thinks that those bozo analists are objective, hard working, number crunching, saints of the financial/ press world, I would suggest you go to the kiddy section of your local video store and get addition information from Bugs Bunny, Mary Poppins, and Wilily Coyote.<BR/><BR/> NO one ever asks these self proclaimed wizards of the financial world what their positions are! Well, some may say that’s too personal and not for public discloser. They will not tell you what they do with THEIR money, yet they can freely suggest what you can do with yours! This comes, of course, with the appropriate and legally mandated disclaimer. Read: If you lose your balls, don’t blame me/us! THERE IS NO ACCOUNTABILITY WHEN THESE GUYS ARE WRONG! It’s just on to the next recommendation, “aah, what I said yesterday doesn’t mater today, what maters is what I am saying about TOMMOROW!!!” Besides, if they’re so brilliant why aren’t they driving the Bentley convertibles?<BR/><BR/>Look, one f**king MORON at Morgan Stanley, Mike Dipshits, decided he was going single handedly bring down all the tech leaders in one day by merely suggesting chip sales would be soft in 4Q 2007, thru 1Q 2008. Maybe he felt the sector needed a correction. Perhaps, he wanted some movement to generate some commissions for the brokers. Meanwhile, back on earth, the actual 3rd quarter numbers revealed chip demand has never been greater, worldwide!!!!. In fact now Anal-Licks are downgrading INTC because of chip shortages due to high demand!!! Well, which the F**K WAY IS IT? <BR/><BR/>They have been downgrading INTC for 3 quarters due to “Lower Margins” straight in the face of nearly 2 billion dollar quarterly profits, strong product lineup, a couple of NEW state of the art fabricating facilities, a 10% reduction in work force, AND a record 10.1 billion in 3rd quarter sales ! What the hell do these guys need, Braille and cane? Close to 40 Billion in yearly sales, 45nM power sipping 214 sq. mm supercomputers, 1 GHz overhead, share price up 35% and INTC doesn’t look good? GMAFB. These guys may as well work for AMD!!!<BR/><BR/>Then, there is the absolutely ultimate mind numbing AMD recommendations. Here is a company that lost close to 15B in 12 months. $15,000,000,000!!!!!!! Their product lineup is an absolute 65nM, antiquated FAILURE by industry standards. Their product has been relegated to the bargain bin sector of the chip world with none, nada, zip, squat, ziltch, nyet, no, profit!!!! NONE IN SIGHT! <BR/><BR/>AMD probably has, from what I read, from the insiders on this site, the worst possible worlds of very low yields on a very shaky process, compounded by a simultaneously implemented, new, and unproven architecture. 1 volt @ 2.4 GHz with 130 watt thermals! I’ve got a Q6600, as I type, that will do half that, at the same speed, at 1.3 volts, HELLO! This Barcelona abomination is leaking power like the Titanic was leaking water. Further, if I read my GURU correctly there ain’t anything they can do to stop it.<BR/><BR/>Let us not even get into the Nvidia vs. AMD thing; there is just no competition there, either. Further, NVDA is NOT going to lay down for AMD, INTC, or anyone. They have the high end market cornered and AMD MUST PRICE THEIR PRODUCTS ACCORDING TO NVDA PERFORMACE LINEUP! READ LOWER MARGINS!!!!<BR/><BR/>Therefore, AMD with all this factored in, must look GOOD!?!? <BR/><BR/><BR/>Do you know where the Titanic is presently located? Ask the Analysts, they may tell you in the Smithsonian Institution, that’s in 2009, of course! They are going down 15000 ft. with a salvation submarine named FUSION and bring it up all in one piece. After all, they have to justify the 5.5 billion dollar ATI iceberg/ catastrophe, and how wrong they all have been all along. <BR/><BR/>SPARKSAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-55636860641297667752007-11-02T20:27:00.000+00:002007-11-02T20:27:00.000+00:00HVM = high volume manufacturing. Don't ever confu...HVM = high volume manufacturing. <BR/><BR/>Don't ever confuse what AMD does with high volume manufacturing. Having a 1/2 - 3/4 filled 300mm fab does not put you into high volume manufacturing. <BR/><BR/>The problem is that because AMD only has one fab on a specific process they think they can tweak and "APM" it on the fly. If they actually had a second fab running a similar process, I think they would be more disciplined (they would have to be) about their manufacturing execution. <BR/><BR/>When you have such small volumes, piloting a change is more or less he same as converting the entire line. With 300mm the # of tools on certain steps shrink - you may only have 2 tools total for certain process steps. If you make a change to one of them...better hope it works!Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-30290488414110469442007-11-02T20:21:00.000+00:002007-11-02T20:21:00.000+00:00"I can understand AMD's, um... carefully worded st..."I can understand AMD's, um... carefully worded statements to the press and to analysts."<BR/><BR/>I should say the issue is with the analysts - AMD is just trying to put lipstick on a pig. The analysts look at that pig and see a supermodel because they are told "it's a supermodel" by AMD.<BR/><BR/>Analysts are supposed to ANALYZE no? They just take everything a company tells them and pass it on without questioning it? The same thing held with Intel in the MHz/GHz war days - rather than trying to analyze the current situation themselves they just take what the companies tell them.<BR/><BR/>AMD says they are ramping in H1'08...great...what does it mean? Who cares they are "ramping in H1'08", that = good, right? Another nice job by the press.<BR/><BR/>At least AMD has seemed to learn a bit about the PR/spin game - the next lesson they will need to learn though is you can only spin so many times before someone will ask you to back it up or your credibility is completely lost. 65nm, 4x4, graphics card delays in order to do a "hard launch", mid-year K10 introduction (@2.6GHz), 40% better K10, higher speed K10's in Q4... AMD is quickly approaching the point where the press or an analyst is going to wake up and say didn't you promise this, this and that and not deliver on it? Why should I believe you anymore?Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-31898806979896966102007-11-02T16:48:00.000+00:002007-11-02T16:48:00.000+00:00Big Die + new architecture + crappy process = dela...<I>Big Die + new architecture + crappy process = delayed launch and low clockspeeds. </I><BR/><BR/><I>Of course the major problem with this is by AMD saying "ramping in H1'08" this actually means they will be installing and qualifying equipment.</I><BR/><BR/>Yes, AMD is certainly breaking one of the cardinal rules of semiconductors, new designs and new processes at the same time do not make for a happy validation process.<BR/><BR/>To be fair, you have to cut AMD a little slack. It's not so much that AMD's process is "crappy" it's more of the problem that they began HVM on an immature process only to "refine" it later. AMD and Intel are both trying to be successful business's and must make all their technical decisions with the business in mind. <BR/><BR/>Due to Intel's vast R&D budget and manufacturing capabilities, it doesn't make sense to start making product as soon as a process is functional. It is far more beneficial for them to wait until the process is mature and begin HVM when it is more practical and cheaper to do so when yields are high and process variation is low. <BR/><BR/>AMD does not have this luxury, even though it doesn't bring them the same economies of scale as Intel, their hand is forced into ramping product on an immature process in order to convince the market they are on equal technological footing. So, they begin production as soon as the process is functional, not when it is necessarily manufacturable. As a result, they must work out all the problems on the fly while and compromise resources on keeping the fleet full to capacity and refining the process at the same time. <BR/><BR/>This gives AMD the appearance of launching 65nm only a few quarters behind Intel, when in fact, process maturity is more than 18 months behind. This game will continue on 45nm when they begin "ramping" in H1'08 less than 6 months after Intel!!!! It should be noted that according to Hector Ruiz's doublespeak, Intel was "ramping" 45nm in Q3'06.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-56084170253267420752007-11-02T13:32:00.000+00:002007-11-02T13:32:00.000+00:00I can understand AMD's, um... carefully worded sta...I can understand AMD's, um... carefully worded statements to the press and to analysts. You would rather give them something to chew on and speculate about (even if it's pretty obvious what is going on) than to flat out admit that things are going badly, because this can snowball into a launch that is a disaster.<BR/><BR/>However, if you are going to do this, especially over a long and agonizing period of time during which your competitor seems to be firing on all cylinders, then you need to deliver on your promises or better. After months of PR-speak and eye-winking at press and analysts, producing CPUs that are running slower than anticipated is potentially crippling for AMD.<BR/><BR/>A week before Phenom hits the streets at lower-than-expected clock speeds, Penryn will hit the street at the announced speeds and with the impression that it is a beast of an overclocker. If Phenom doesn't show some real overclocking promise (and there is reason to assume that it will not), it may hit the enthusiast segment with a barely-audible thud.Tonushttps://www.blogger.com/profile/01082528970434639776noreply@blogger.comtag:blogger.com,1999:blog-2602471396566186819.post-65231878450576763472007-11-02T12:30:00.000+00:002007-11-02T12:30:00.000+00:00Phenom launched slowed to 2.4GHz now. http://www.t...Phenom launched slowed to 2.4GHz now. <BR/><BR/>http://www.theinquirer.net/gb/inquirer/news/2007/11/02/phenom-slowed-again<BR/><BR/>I think it's fairly safe to say now that the fastest Phenom X4 will be slower than the slowest C2Q 6600?Epsilonhttps://www.blogger.com/profile/03815428867077063484noreply@blogger.com